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公开(公告)号：US20190319538A1
公开(公告)日：2019-10-17
申请号：US16385284
申请日：2019-04-16
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号：US20190267991A1
公开(公告)日：2019-08-29
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G05B11/42 , G01R19/165
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US20190235551A1
公开(公告)日：2019-08-01
申请号：US16381541
申请日：2019-04-11
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
CPC classification number: G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H01R2107/00 , H02J7/022 , H02J7/06 , H02J2007/10 , H03F3/45071 , H03F2203/45521 , H03F2203/45641
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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公开(公告)号：US10359800B2
公开(公告)日：2019-07-23
申请号：US15693214
申请日：2017-08-31
Inventor： Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
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公开(公告)号：US10303192B2
公开(公告)日：2019-05-28
申请号：US15364392
申请日：2016-11-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
IPC: H02J7/00 , G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H02J7/02 , H02J7/06 , H03F3/45 , H01R107/00 , H02J7/10
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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Patent Agency Ranking
公开(公告)号：US10254781B2
公开(公告)日：2019-04-09
申请号：US15722404
申请日：2017-10-02
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno Lenz
Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.
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公开(公告)号：US20190094895A1
公开(公告)日：2019-03-28
申请号：US16130706
申请日：2018-09-13
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno Lenz
Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.
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公开(公告)号：US20190074763A1
公开(公告)日：2019-03-07
申请号：US16103582
申请日：2018-08-14
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
Abstract: A method can be used for compensating a voltage drop on a cable connected between a source device and a receiver device. The source device delivers an offset current on a channel configuration pin of the source device, the offset current causing an increase in a voltage on the channel configuration pin of the source device to a chosen reference voltage. The offset current is stored in the source device. The source device absorbs an absorption current originating from the channel configuration pin of the source device, the absorption current depending on the stored offset current and on the voltage drop. The source device generates a compensated supply voltage on a power supply pin of the source device, the compensated supply voltage equal to a reference supply voltage increased by the voltage drop to within a tolerance.
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公开(公告)号：US20190067180A1
公开(公告)日：2019-02-28
申请号：US16110121
申请日：2018-08-23
Inventor： David AUCHERE , Laurent SCHWARZ , Deborah COGONI , Eric SAUGIER
IPC: H01L23/498 , H01L23/31 , H01L23/13 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/561 , H01L21/78 , H01L23/13 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L23/5389 , H01L24/00 , H01L24/16 , H01L24/97 , H01L2224/16227 , H01L2224/16235 , H05K1/185 , H05K2201/10621 , H05K2201/10636
Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
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70.发明申请公开(公告)号：US20190027925A1
公开(公告)日：2019-01-24
申请号：US16026503
申请日：2018-07-03
Applicant: STMicroelectronics(Alps) SAS
Inventor： Frederic Lebon , Laurent Chevalier
Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
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