公开(公告)号：US20230349969A1

公开(公告)日：2023-11-02

申请号：US18186549

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma ,  Samiksha Agarwal

IPC: G01R31/317

CPC classification number: G01R31/31703 ,  G01R31/31722

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

公开(公告)号：US11782095B2

公开(公告)日：2023-10-10

申请号：US17368198

申请日：2021-07-06

Applicant: STMicroelectronics Application GMBH

Inventor： Markus Ekler

IPC: G01R31/382 ,  G01R31/396 ,  G01R31/367 ,  B60L58/12 ,  H01M10/42

CPC classification number: G01R31/382 ,  B60L58/12 ,  G01R31/367 ,  G01R31/396 ,  H01M10/4257 ,  H01M2010/4271 ,  H01M2220/20

Abstract: An embodiment processing system comprises terminals configured to be connected to cells of a rechargeable battery to receive cell voltages, a digital processing circuit, a serial communication interface and a transmission queue interfacing the digital processing circuit with the serial communication interface for parallel operation. The digital processing circuit synchronously acquires a given number of digital samples of each of the cell voltages and stores them to a memory. The digital processing circuit encodes the digital samples stored to the memory via a data compression module, and stores the encoded data to the transmission queue. For example, the data compression module may generate the encoded data by subtracting a given offset from each digital sample to generate values indicative of the dynamic variation of each sample with respect to the offset, and removing a given number of most significant bits from each value.

公开(公告)号：US20230299999A1

公开(公告)日：2023-09-21

申请号：US18320764

申请日：2023-05-19

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred RENNIG ,  Rolf NANDLINGER

IPC: H04L12/40 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4022 ,  G06F13/426 ,  H04L12/40169 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US11755062B2

公开(公告)日：2023-09-12

申请号：US17933680

申请日：2022-09-20

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger

IPC: G06F1/14

CPC classification number: G06F1/14

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

公开(公告)号：US20220357973A1

公开(公告)日：2022-11-10

申请号：US17736590

申请日：2022-05-04

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

Inventor： Boris VITTORELLI ,  Simrata BATRA ,  Vivek Kumar SOOD ,  Deepak BARANWAL

IPC: G06F9/455

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

公开(公告)号：US11483909B2

公开(公告)日：2022-10-25

申请号：US17523641

申请日：2021-11-10

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application S.R.O.

Inventor： Donato Tagliavia ,  Vincenzo Polisi ,  Calogero Andrea Trecarichi ,  Francesco Nino Mammoliti ,  Jochen Barthel ,  Ludek Beran

IPC: H05B45/10 ,  H05B45/38 ,  H05B45/46 ,  H05B45/375

Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.

公开(公告)号：US11480994B2

公开(公告)日：2022-10-25

申请号：US16857544

申请日：2020-04-24

Applicant: STMicroelectronics Application GmbH

Inventor： Rolf Nandlinger

IPC: G06F1/14

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

公开(公告)号：US20220214430A1

公开(公告)日：2022-07-07

申请号：US17568317

申请日：2022-01-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： Romeo LETOR ,  Roberto TIZIANI ,  Alfio RUSSO ,  Antoine PAVLIN ,  Nadia LECCI ,  Manuel GAERTNER

IPC: G01S7/484 ,  G01S7/481

Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

公开(公告)号：US20210382779A1

公开(公告)日：2021-12-09

申请号：US17406910

申请日：2021-08-19

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/07 ,  G06F11/10

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

公开(公告)号：US11113136B2

公开(公告)日：2021-09-07

申请号：US16289405

申请日：2019-02-28

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.