公开(公告)号：KR100650698B1

公开(公告)日：2006-11-27

申请号：KR1020050070499

申请日：2005-08-02

Applicant: 삼성전자주식회사

Inventor： 전택수 ,  신유균 ,  강상범 ,  조학주 ,  이혜란 ,  김상용

IPC: H01L27/092 ,  H01L27/088 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device is provided to restrain the degradation of dielectric characteristics and to control uniformly the thickness of first and second metallic gates using an enhanced dual gate structure. A dielectric film(102a,102b) is formed on a semiconductor substrate(100). A first metallic conductive layer with a first thickness is formed on the dielectric film. An etch rate of the first metallic conductive layer is decreased by annealing. A second metallic conductive layer with a second thickness larger than the first thickness is formed on the first metallic conductive layer. The second metallic conductive layer is selectively removed from a second region of the substrate by using an etch selectivity between the first and second metallic conductive layers. At this time, a first gate stack structure(115) with a first metallic gate(110) is formed on a first region of the substrate and a second gate stack structure(120) with a second metallic gate(104b) is formed on the second region of the substrate.

Abstract translation: 提供了一种用于制造半导体器件的方法，以抑制介电特性的退化并且使用增强的双​​栅极结构来均匀地控制第一和第二金属栅极的厚度。 介电膜（102a，102b）形成在半导体衬底（100）上。 具有第一厚度的第一金属导电层形成在电介质膜上。 第一金属导电层的刻蚀速率通过退火而降低。 在第一金属导电层上形成具有大于第一厚度的第二厚度的第二金属导电层。 通过使用第一和第二金属导电层之间的蚀刻选择性，从衬底的第二区域选择性地去除第二金属导电层。 此时，具有第一金属栅极（110）的第一栅极堆叠结构（115）形成在衬底的第一区域上，具有第二金属栅极（104b）的第二栅极堆叠结构（120）形成在 衬底的第二区域。

公开(公告)号：KR100641074B1

公开(公告)日：2006-11-01

申请号：KR1020050092797

申请日：2005-10-04

Applicant: 삼성전자주식회사

Inventor： 조학주 ,  신유균 ,  강상범 ,  전택수 ,  이혜란

IPC: H01L27/115