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公开(公告)号：KR1020030079425A
公开(公告)日：2003-10-10
申请号：KR1020020018448
申请日：2002-04-04
Applicant: 삼성전자주식회사
IPC: G11C16/06
CPC classification number: G11C7/04 , G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/3459
Abstract: PURPOSE: A multi bit flash memory having a temperature compensation function is provided to control threshold voltage distribution optimally and to perform a reliable read operation without regard to temperature variation. CONSTITUTION: According to the semiconductor memory device having memory cells storing a plurality of data, word lines and bit lines are connected to the above memory cells. A circuit(30) supplies a temperature dependent voltage to the above selected word line to read a state of the above memory cell. And a circuit(20) supplies a voltage to the above unselected word lines to read the state of the memory cell. The circuit supplying the temperature dependent voltage comprises a semiconductor device whose resistance varies according to the temperature.
Abstract translation: 目的：提供具有温度补偿功能的多位闪存，以最佳地控制阈值电压分布，并且不考虑温度变化执行可靠的读取操作。 构成：根据具有存储多个数据的存储单元的半导体存储器件，将字线和位线连接到上述存储单元。 电路（30）向上述选择的字线提供与温度有关的电压，以读取上述存储单元的状态。 并且电路（20）向上述未选择的字线提供电压以读取存储器单元的状态。 提供温度依赖电压的电路包括其电阻根据温度而变化的半导体器件。
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公开(公告)号：KR100382729B1
公开(公告)日：2003-05-09
申请号：KR1020000074916
申请日：2000-12-09
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76804 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , H01L2924/00
Abstract: A metal contact structure of a semiconductor device and a method for forming the same are provided. The diameter of the upper portion of a contact hole that exposes a region of a lower conductive layer is formed to be larger than the diameter of the lower portion of the contact hole. The metal contact structure is formed without a void or a key hole. This is accomplished by forming at least two metal layers to fill the contact hole by performing a first deposition, an etch back, and a second deposition. The metal layer which fills the contact hole is etched back using a barrier metal layer formed on the entire surface of the contact hole as an etching stop layer. Thus, a void or key hole is not generated by making the upper portion of the contact hole to be wider than the lower portion of the contact hole and by depositing the metal which fills the contact hole through the processes of firstly depositing the metal, etching back the metal, and secondly depositing the metal.
Abstract translation: 提供了一种半导体器件的金属接触结构及其形成方法。 暴露下导电层的区域的接触孔的上部的直径形成为大于接触孔的下部的直径。 金属接触结构形成为没有空隙或钥匙孔。 这通过形成至少两个金属层以通过执行第一沉积，回蚀和第二沉积来填充接触孔来实现。 使用形成在接触孔的整个表面上的阻挡金属层作为蚀刻停止层来回蚀填充接触孔的金属层。 因此，通过使接触孔的上部比接触孔的下部宽，并且通过首先沉积金属的工艺沉积填充接触孔的金属，不会产生空隙或键孔，蚀刻 倒回金属，然后沉积金属。
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公开(公告)号：KR1020030003906A
公开(公告)日：2003-01-14
申请号：KR1020010039762
申请日：2001-07-04
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
Abstract: PURPOSE: A method for fabricating a contact of a semiconductor device is provided to remarkably reduce contact resistance by eliminating the necessity of a self-aligned contact(SAC) process in forming the contact so that damage to a specific underlying layer or semiconductor substrate exposed to the lower portion of a contact hole is minimized. CONSTITUTION: A plurality of the first conductive patterns adjacent to each other are formed on a semiconductor substrate(40). The first spacer(52) of an insulation property is formed on the respective sidewalls of the first conductive patterns. A predetermined thickness of a photoresist layer is formed on the first conductive pattern, filling the gap between the first conductive patterns. A photoresist pattern(54') covering a contact formation region between the first conductive patterns is formed. The first insulation material layer having etch selectivity on the photoresist is formed in a region except where the photoresist pattern is formed. The photoresist pattern is eliminated. The contact made of the first conductive material layer is formed in the contact formation region where the photoresist pattern is removed.
Abstract translation: 目的：提供一种用于制造半导体器件的接触的方法，通过消除在形成接触时需要进行自对准接触（SAC）处理以显着降低接触电阻，使得暴露于 接触孔的下部被最小化。 构成：在半导体衬底（40）上形成有彼此相邻的多个第一导电图案。 在第一导电图案的相应侧壁上形成绝缘性的第一间隔物（52）。 在第一导电图案上形成光致抗蚀剂层的预定厚度，填充第一导电图案之间的间隙。 形成覆盖第一导电图案之间的接触形成区域的光致抗蚀剂图案（54'）。 在光致抗蚀剂图案之外的区域中形成具有在光刻胶上的蚀刻选择性的第一绝缘材料层。 消除光致抗蚀剂图案。 由第一导电材料层制成的触点形成在除去光致抗蚀剂图案的接触形成区域中。
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公开(公告)号：KR1020020093240A
公开(公告)日：2002-12-16
申请号：KR1020010031700
申请日：2001-06-07
Applicant: 삼성전자주식회사
Inventor： 조태희
IPC: H01L21/3205
CPC classification number: H01L21/76804 , H01L21/76838 , H01L21/7684 , H01L21/76852 , H01L21/76885 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor device having a multilevel interconnection structure is provided to reduce contact resistance by increasing a contact area between a contact stud and the second metal interconnection layer, and to extend the lifetime of interconnection by increasing a contact area between the contact stud and the second metal interconnection layer even if a void is formed near the contact stud by electromigration. CONSTITUTION: The first metal interconnection layer(24) is formed on a semiconductor substrate(10). The second metal interconnection layer is formed on the first metal interconnection layer. An intermetal dielectric is interposed between the first and second metal interconnection layer. The contact stud(49) electrically connects the first metal interconnection layer with the second metal interconnection layer. The contact stud is composed of the first portion(47) penetrating the intermetal dielectric and the second portion(48) formed in a position higher than the intermetal dielectric. The second portion has a vertical sidewall vertically extending with respect to a main surface of the semiconductor substrate and an upper surface extending in parallel with the main surface of the semiconductor substrate. The vertical sidewall and the upper surface are covered with the second metal interconnection layer.
Abstract translation: 目的：提供具有多层互连结构的半导体器件，以通过增加接触柱和第二金属互连层之间的接触面积来减小接触电阻，并通过增加接触柱和第二金属互连层之间的接触面积来延长互连的寿命 第二金属互连层，即使通过电迁移在接触柱附近形成空隙。 构成：第一金属互连层（24）形成在半导体衬底（10）上。 第二金属互连层形成在第一金属互连层上。 在第一和第二金属互连层之间插入金属间电介质。 接触柱（49）将第一金属互连层与第二金属互连层电连接。 接触柱由穿过金属间电介质的第一部分（47）和形成在高于金属间电介质的位置的第二部分（48）组成。 第二部分具有相对于半导体衬底的主表面垂直延伸的垂直侧壁和与半导体衬底的主表面平行延伸的上表面。 垂直侧壁和上表面被第二金属互连层覆盖。
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公开(公告)号：KR1020020065214A
公开(公告)日：2002-08-13
申请号：KR1020010005634
申请日：2001-02-06
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a contact hole of a semiconductor device is provided to minimize time for a photo process and an etch process and form the contact hole without an additional process for removing a spacer. CONSTITUTION: The first insulating layer(12) is formed on a substrate(10). A resist layer and a resist pattern are formed thereon. A recess region(20) is formed by etching the first insulating layer(12). The resist pattern is removed therefrom. The second insulating layer is formed on the recess region(20) and the first insulating layer(12). A spacer(23) is formed on a sidewall of the recess region(20) by etching the second insulating layer. A contact hole(24) is formed by etching the first insulating layer(12). A diameter of the contact hole(24) is controlled by using thickness of the second insulating layer.
Abstract translation: 目的：提供一种用于形成半导体器件的接触孔的方法，以最小化光刻工艺和蚀刻工艺的时间，并形成接触孔，而不需要用于移除间隔物的附加工艺。 构成：第一绝缘层（12）形成在基板（10）上。 在其上形成抗蚀剂层和抗蚀剂图案。 通过蚀刻第一绝缘层（12）形成凹陷区域（20）。 从中除去抗蚀剂图案。 第二绝缘层形成在凹部区域（20）和第一绝缘层（12）上。 通过蚀刻第二绝缘层，在凹部区域（20）的侧壁上形成间隔物（23）。 通过蚀刻第一绝缘层（12）形成接触孔（24）。 通过使用第二绝缘层的厚度来控制接触孔（24）的直径。
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Patent Agency Ranking
公开(公告)号：KR1020010029546A
公开(公告)日：2001-04-06
申请号：KR1020000000497
申请日：2000-01-06
Applicant: 삼성전자주식회사
IPC: G11C16/02
Abstract: PURPOSE: A nonvolatile semiconductor memory device and method for programming the memory device are provided to prevent yield from being degraded by a failed column. CONSTITUTION: The memory device includes a memory cell array(100), a read circuit, a column selecting circuit, an address generating circuit(120) and a program state detecting circuit(190). The memory cell array provides a plurality of memory cells which are arranged in each of a plurality of rows, a plurality of columns and the crossing area of the rows and the columns. The read circuit reads programmed data bits from the memory cell array through the columns and then latches the read programmed data bits. The column selecting circuit selects part of the columns in response to a column address. The address generating circuit generates the column address in response to a pulse signal. The program state detecting circuit generates the pulse signal by judging to have or not program state for all of data bits outputted from the column selecting circuit during a program pass/fail judgement operation of a program cycle is performed.
Abstract translation: 目的：提供用于对存储器件进行编程的非易失性半导体存储器件和方法，以防止失败的色谱柱降低成品率。 构成：存储器件包括存储单元阵列（100），读取电路，列选择电路，地址生成电路（120）和程序状态检测电路（190）。 存储单元阵列提供多个存储单元，其布置在多行，多列和行和列的交叉区域中的每一行中。 读取电路通过列读取存储单元阵列中的编程数据位，然后锁存读取的编程数据位。 列选择电路响应列地址选择列的一部分。 地址产生电路响应于脉冲信号产生列地址。 程序状态检测电路通过在执行程序循环的程序通过/失败判断操作期间判断是否具有从列选择电路输出的所有数据位的编程状态来生成脉冲信号。
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公开(公告)号：KR1019990048711A
公开(公告)日：1999-07-05
申请号：KR1019970067477
申请日：1997-12-10
Applicant: 삼성전자주식회사
Inventor： 조태희
IPC: G06F9/06
Abstract: 가.청구범위에 기재된 발명이 속한 기술분야
개인용 컴퓨터에서 로그-인시 사용자 확인방법에 관한 것이다.
나.발명이 해결하려고 하는 기술적 과제
개인용 컴퓨터에서 인가받지 않은 사용자는 패스워드를 입력시킨다해도 개인용 컴퓨터에 접속할 수 없도록 효과적으로 막을 수 있는 사용자 확인 방법을 제공함에 있다.
다.발명의 해결방법의 요지
미리 인가받은 사용자의 키보드 입력속도에 따른 키보드 입력패턴을 저장시켜 두었다가 로그-인시 사용자 확인을 거친 사용자라 할지라도 상기 미리 저장된 키보드 입력 패턴과 다른 키보드 입력패턴을 보인다면 사용자 및 관리자에게 경고메시지를 보내거나 강제로 접속을 끊음으로써 개인용 컴퓨터의 사용을 중지시킴을 특징으로 한다.
라.발명의 중요한 용도
개인용 컴퓨터에서 로그-인시 인가받은 사용자인지를 확인할 때 이용한다.-
公开(公告)号：KR102053353B1
公开(公告)日：2019-12-09
申请号：KR1020130079029
申请日：2013-07-05
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8234 , H01L21/28 , H01L21/768
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公开(公告)号：KR1020150005817A
公开(公告)日：2015-01-15
申请号：KR1020130079029
申请日：2013-07-05
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242 , H01L21/764
CPC classification number: H01L27/10855 , H01L21/28132 , H01L21/76838 , H01L21/76897 , H01L21/823468
Abstract: 반도체 소자는, 복수의 활성 영역을 가지는 기판과, 상기 복수의 활성 영역 위에 형성되고 제1 측벽 및 제2 측벽을 가지는 도전 패턴과, 상기 복수의 활성 영역 위에서 제1 에어 스페이서(air spacer)를 사이에 두고 상기 도전 패턴의 제1 측벽에 대면하고 제1 방향으로 연장되는 제1 도전 라인, 및 상기 복수의 활성 영역 위에서 제2 에어 스페이서를 사이에 두고 상기 도전 패턴의 제2 측벽에 대면하고 상기 제1 방향으로 연장되는 제2 도전 라인을 포함하고, 상기 제1 에어 스페이서 내에서는 상기 제1 도전 라인이 노출된다.
Abstract translation: 半导体器件包括：衬底，其包括多个有源区; 形成在有源区上并包括第一侧壁和第二侧壁的导电图案; 第一导电线，其通过在所述有源区上插入第一空气隔离物并且沿第一方向延伸而面对所述导电图案的所述第一侧壁; 以及第二导线，其通过在所述有源区上插入第二空气隔离物并沿所述第一方向延伸而面向所述导电图案的所述第二侧壁。 第一导电线暴露在第一空气间隔件中。
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公开(公告)号：KR1020130103173A
公开(公告)日：2013-09-23
申请号：KR1020120024597
申请日：2012-03-09
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A method and an apparatus thereof for reducing a delay which is caused by a reception path calibration are provided to reduce a signal distortion which is caused by a reception direct current (DC) in a radio communication system which uses a multiband. CONSTITUTION: Each of mixers (102-I,102-Q) converts a reception signal into a base band signal by using a frequency which is provided from a local oscillator. Each of DC compensators (106-I,106-Q) includes an operational amplifier and a low pass filter. Each of the DC compensators compensates a DC which is included in an output signal of a frequency converter by controlling the pass band size of the low pass filter. Each of the DC compensators feeds back the output of the operational amplifier as an input by using the low pass filter. [Reference numerals] (104) Local oscillator; (106-I,106Q) DC compensator; (112-I1,112-Q1) Connection controller 1; (112-IN,112-QN) Connection controller N; (116-I,116-Q) Buffer; (120) Baseband zone processing unit; (124-Q,124-I) Switch; (126-Q,126-I) Modem; (128-Q,128-I) Calibration module; (130) I channel RF processor; (140) Q channel RF processor; (150) I channel baseband zone processing unit; (160) Q channel baseband zone processing unit; (300) RF processor
Abstract translation: 目的：提供一种用于减少由接收路径校准引起的延迟的方法和装置，以减少在使用多频带的无线电通信系统中由接收直流（DC）引起的信号失真。 构成：混频器（102-I，102-Q）中的每一个通过使用从本地振荡器提供的频率将接收信号转换成基带信号。 每个DC补偿器（106-I，106-Q）包括运算放大器和低通滤波器。 每个DC补偿器通过控制低通滤波器的通带尺寸来补偿包含在变频器的输出信号中的DC。 每个直流补偿器通过使用低通滤波器反馈运算放大器的输出作为输入。 （附图标记）（104）本地振荡器; （106-I，106Q）直流补偿器; （112-I1,112-Q1）连接控制器1; （112-IN，112-QN）连接控制器N; （116-I，116-Q）缓冲液; （120）基带区处理单元; （124-Q，124-I）开关; （126-Q，126-I）调制解调器; （128-Q，128-I）校准模块; （130）I通道射频处理器; （140）Q通道RF处理器; （150）I信道基带区处理单元; （160）Q信道基带区处理单元; （300）射频处理器
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