公开(公告)号：KR100429077B1

公开(公告)日：2004-04-29

申请号：KR1020010071309

申请日：2001-11-16

Applicant: 한국전자통신연구원

Inventor： 이승철 ,  권종기 ,  김귀동 ,  김경수

IPC: H03M1/66

CPC classification number: H03K17/102 ,  H03K17/04106 ,  H03M1/742

Abstract: The present invention relates to a current cell driving circuit in a digital-to-analog converter. The current cell driving circuit limits the potential of differential control signals to a given potential level by means of a voltage limiter using a parasitic capacitance of a transistor. Therefore, the present invention can effectively limit the potential of differential control signals DP and DN without compromising the power consumption and the circuit area and also can minimize the transfer time.

Abstract translation: 本发明涉及数模转换器中的电流单元驱动电路。 电流单元驱动电路借助于使用晶体管的寄生电容的电压限制器将差分控制信号的电位限制到给定的电位电平。 因此，本发明可以有效地限制差分控制信号DP和DN的潜力，而不损害功耗和电路面积，并且还可以使传输时间最小化。

公开(公告)号：KR100422806B1

公开(公告)日：2004-03-16

申请号：KR1020010065158

申请日：2001-10-22

Applicant: 한국전자통신연구원

Inventor： 김귀동 ,  정희범

IPC: H03K19/00

Abstract: PURPOSE: A current controlled variable delay circuit is provided to have low phase noise and a high speed switching. CONSTITUTION: The current controlled variable delay circuit comprises a variable current source(500), and a switching transistor part(100) forming a current path between the variable current source and one of the first and the second differential output signal(+Vout,-Vout) of the first or the second potential level in response to the first and the second differential input signal(V+,V-). A differential signal sensing part(200) generates the first and the second differential output signal by amplifying a different between the first and the second differential input signal in response to an output of the switching transistor part and operates in a saturated region. A positive feedback amplification part(300) increases a sensing speed of the differential signal sensing part by receiving an output of the differential signal sensing part as an input. And a potential level decreasing part(400) reduces noise of the first and the second differential output signal by reducing a potential difference between the first and the second differential output signal, and increases a response speed of the first or the second differential output signal responding to the first and the second differential input signal.

Abstract translation: 目的：提供电流控制的可变延迟电路以具有低相位噪声和高速切换。 构成：电流控制可变延迟电路包括可变电流源（500）和形成可变电流源与第一和第二差分输出信号（+ Vout， - 响应于第一和第二差分输入信号（V +，V-），输出第一或第二电位电平。 差分信号感测部分（200）响应于开关晶体管部分的输出通过放大第一差分输入信号和第二差分输入信号之间的差而产生第一差分输出信号和第二差分输出信号，并且操作在饱和区中。 正反馈放大部分（300）通过接收差分信号感测部分的输出作为输入来增加差分信号感测部分的感测速度。 并且电位降低部（400）通过减小第一和第二差分输出信号之间的电位差来减小第一和第二差分输出信号的噪声，并且增加第一或第二差分输出信号响应的响应速度 到第一和第二差分输入信号。

公开(公告)号：KR100377477B1

公开(公告)日：2003-03-26

申请号：KR1019990037893

申请日：1999-09-07

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 송원철 ,  정희범 ,  김귀동 ,  김성도

IPC: H03B5/12

Abstract: PURPOSE: A voltage-controlled oscillator having linear characteristic is provided to make a variation rate uniform without regard to a control voltage, so improve the characteristic of PLL. CONSTITUTION: The device includes a voltage-to-current converter(110) for converting an input control voltage into current, a current providing unit(120) for providing the converted current to an oscillator(130), and a voltage restricting unit(140) for restricting the voltage of the oscillator. The oscillator accepts the converted current to oscillate. The voltage-to-current converter has a buffer for compensating for a threshold voltage at the input port to operate normally from the initial operation state. The converter operates a transistor taking charge of conversion in a linear area to make a voltage/current conversion gain be linear.

Abstract translation: 目的：提供具有线性特性的电压控制振荡器，使变化率不受控制电压影响，从而改善PLL的特性。 该装置包括用于将输入控制电压转换为电流的电压 - 电流转换器（110），用于将转换后的电流提供给振荡器（130）的电流提供单元（120），以及电压限制单元 ）用于限制振荡器的电压。 振荡器接受转换后的电流进行振荡。 电压 - 电流转换器具有缓冲器，用于补偿输入端口处的阈值电压以从初始操作状态正常操作。 转换器在线性区域中操作负责转换的晶体管以使电压/电流转换增益为线性。

公开(公告)号：KR100373322B1

公开(公告)日：2003-02-25

申请号：KR1020000086651

申请日：2000-12-30

Applicant: 한국전자통신연구원

Inventor： 서혜주 ,  권종기 ,  김귀동 ,  정희범

IPC: H03H11/02

Abstract: PURPOSE: An automatic frequency tuning circuit for correcting an influence of offset for transistor conductance-capacitor filter is provided to control correctly a band frequency of a filter by correcting offset of a tuning circuit. CONSTITUTION: A reference power supply portion(100) provides reference power. A Gm amplifier(5) has. The first integrator(200) has a Gm amplifier(5) having the same as a Gm value of a controlled filter in order to generate periodically charge voltage and discharge voltage proportional to offset of the Gm amplifier(5) in response to the reference power. The second integrator(300) has a Gm amplifier(16) having the same as a Gm value of a controlled filter in order to generate periodically charge voltage and proportional to offset of the Gm amplifier(16) in response to the output voltage(Vo1) of the first integrator(200) and discharge voltage proportional to offset of the Gm amplifier(16) in response to the reference power. A sampling portion(400) samples periodically the output voltage of the second integrator(300). An output portion(500) outputs the sampled voltage of the sampling portion(400) as a tuning signal and feed back the tuning signal to the Gm amplifier(5) in order to control a transfer conductance value of the Gm amplifier(5).

Abstract translation: 目的：提供一种用于校正晶体管电导电容器滤波器的偏移影响的自动频率调谐电路，以通过校正调谐电路的偏移来正确地控制滤波器的频带频率。 构成：参考电源部分（100）提供参考功率。 一个Gm放大器（5）具有。 第一积分器（200）具有与受控滤波器的Gm值相同的Gm放大器（5），以响应于参考功率产生周期性的充电电压和与Gm放大器（5）的偏移成比例的放电电压 。 第二积分器（300）具有与受控滤波器的Gm值相同的Gm放大器（16），以便响应于输出电压（Vo1）产生周期性充电电压并与Gm放大器（16）的偏移成比例 ）以及响应于所述参考功率而放电的电压，所述放电电压与所述Gm放大器（16）的偏移量成比例。 采样部分（400）周期性地采样第二积分器（300）的输出电压。 输出部分（500）输出采样部分（400）的采样电压作为调谐信号，并将调谐信号反馈到Gm放大器（5），以便控制Gm放大器（5）的传输电导值。

公开(公告)号：KR1020010073947A

公开(公告)日：2001-08-03

申请号：KR1020000003156

申请日：2000-01-24

Applicant: 한국전자통신연구원 ,  브이케이 주식회사

Inventor： 김귀동 ,  정희범

IPC: H03L7/00

Abstract: PURPOSE: A high speed and low voltage charge pump of a phase synchronous loop is provided to make the output load of a charge pump high and to make the size of the output current changed automatically according to the loop filter voltage. CONSTITUTION: The high speed and low voltage charge pump(200) of the phase synchronous loop includes many transistors. A source of the charge transistor(M11) is connected to the power voltage(VCC). The gate and drain of a charge bias transistor(M12) are connected to the gate of the charge transistor(M11). The drain of a charge switching transistor(M7) is connected to the drain of the charge bias transistor(M12). The source of a P channel MOS transistor(M10) is connected to the drain of the charge transistor(M11) and the gate and drains are connected the output node(Icm). The gate and drains of an N channel MOS transistor diode(M9) is connected to the output node(Icm). The gate of a discharge switching transistor(M8) is connected to the discharge input signal(DP) and the drain is connected to the source of the N channel MOS transistor diode(M9) and the source of that is connected to the node a. The drain of a discharge bias transistor(M1) is connected to the node a and the source of that is connected to the bias(VSS).

Abstract translation: 目的：提供相位同步环路的高速和低压电荷泵，使电荷泵的输出负载较高，并根据环路滤波器电压自动改变输出电流的大小。 构成：相位同步回路的高速和低压电荷泵（200）包括许多晶体管。 充电晶体管（M11）的源极连接到电源电压（VCC）。 电荷偏置晶体管（M12）的栅极和漏极连接到充电晶体管（M11）的栅极。 充电开关晶体管（M7）的漏极连接到电荷偏置晶体管（M12）的漏极。 P沟道MOS晶体管（M10）的源极连接到充电晶体管（M11）的漏极，栅极和漏极连接在输出节点（Icm）上。 N沟道MOS晶体管二极管（M9）的栅极和漏极连接到输出节点（Icm）。 放电开关晶体管（M8）的栅极连接到放电输入信号（DP），漏极连接到N沟道MOS晶体管二极管（M9）的源极，其源极连接到节点a。 放电偏压晶体管（M1）的漏极连接到节点a，其源极连接到偏置（VSS）。

公开(公告)号：KR100248426B1

公开(公告)日：2000-03-15

申请号：KR1019970070330

申请日：1997-12-19

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 김성도 ,  정희범 ,  김귀동 ,  송원철 ,  김경수

IPC: H04L12/28

Abstract: 본 발명은 SDH 기반의 ATM 통신에서 STM-n(Synchronous Transport Module-n, n=1,4,16..) 타이머의 오류 검출 및 자동 복구를 위한 리셋 신호 생성장치에 관한 것이다. 본 발명은 두 클럭원간의 스위칭 동작을 비트동기장치의 LOS(Loss Of Signal) 정보로부터 감지하고 이 스위칭으로 인하여 디지털회로가 영향을 받았는지를 OOF(Out Of Frame)와 FPID(Framing Word Detection Indication Signal) 정보로부터 판단한 후에 비정상적인 동작상태로 판단되면 리셋신호를 생성하여 STM-n(n=1,4,16) 프레임 데이터의 타이머회로를 초기화시킴으로써 클럭 글리치에 의한 비정상적인 동작상태에서 자동적으로 복구할 수 있도록 고안된 STM-n(n=1,4,16) 프레임 데이터 처리를 위한 타이머회로의 오류검출 및 자동복구를 위한 리셋신호 생성장치에 관한 것이다.

公开(公告)号：KR1019950007348B1

公开(公告)日：1995-07-10

申请号：KR1019920009982

申请日：1992-06-09

Applicant: 한국전자통신연구원 ,  재단법인한국전자통신연구소 ,  주식회사 케이티

Inventor： 김귀동 ,  구용서 ,  한태현 ,  구진근

IPC: H01L29/70

Abstract: an emitter(2) of n+ buried layer(2) formed on a substrate(1); a polysilicon layer(3), an n- epitaxial layer(4), an oxide layer(5), a nitride layer(6) and a low temp. depositing oxide layer grown on the n+ buried layer(2) in turn; an isolation oxide layer(8) grown to be formed on a trench formed by etching the respective growth layer; a field oxide layer(9) formed by selectively growing an active region to position the interface of the oxide layer and the nitride layer at the n+ buried layer(2); a N+ polycrystal silicon electrode and a collector formed by selectively etching the grown layers; a base contact region formed by selective etching of a side wall nitried layer(15); a base electrode formed by growing the P+ polycrystal silicon layer(18); and a metal wiring formed by covering the contact opening with aluminium. The transistor has the increased voltage and the high switching speed in IIL circuit.

Abstract translation: 在衬底（1）上形成的n +掩埋层（2）的发射极（2）; 多晶硅层（3），n外延层（4），氧化物层（5），氮化物层（6）和低温 依次沉积在n +掩埋层（2）上生长的氧化物层; 生长在通过蚀刻各个生长层形成的沟槽上的隔离氧化物层（8）; 通过选择性地生长活性区以在n +掩埋层（2）处定位氧化物层和氮化物层的界面而形成的场氧化物层（9）; 通过选择性蚀刻生长层形成的N +多晶硅电极和集电体; 通过选择性蚀刻侧壁三层（15）形成的基底接触区域; 通过生长P +多晶硅层（18）而形成的基极; 以及通过用铝覆盖接触开口而形成的金属布线。 晶体管在IIL电路中具有增加的电压和高开关速度。

公开(公告)号：KR1019950001147B1

公开(公告)日：1995-02-11

申请号：KR1019910021081

申请日：1991-11-25

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 김귀동 ,  구진근 ,  한태현 ,  구용서

IPC: H01L29/70

Abstract: The method includes the steps of sequentially forming a poly-Si film (1), an oxide film (2), a nitride film (3) and a poly-Si film (4) on the substrate; growing and etching an oxide film (6) to define a device size; forming a trench isolation region (7) and poly-Si electrodes (8,9,10), depositing and etching an LPCVD oxide film thereon to expose the poly-Si films (4,8) to form a trench isolation oxide film (12) to remove the film (4) to form an unactive base electrode (25) with boron doping, growing an oxide film (13) on the electrode (25); removing a nitride film (3) to form diffusion layers (14,15,16,17), and forming a self aligned silicide layer (18) and metallic wirings on the electrode (25,26,27); thereby reducing the parasitic resistance component.

Abstract translation: 该方法包括在基板上依次形成多晶硅膜（1），氧化膜（2），氮化物膜（3）和多晶硅膜（4）的步骤; 生长和蚀刻氧化膜（6）以限定器件尺寸; 形成沟槽隔离区域（7）和多晶硅电极（8,9,10），在其上沉积和蚀刻其上的LPCVD氧化膜以暴露多晶硅膜（4,8）以形成沟槽隔离氧化膜（12 ）以去除所述膜（4）以形成具有硼掺杂的非活性基极（25），在所述电极（25）上生长氧化物膜（13）; 去除氮化物膜（3）以形成扩散层（14,15,16,17），以及在所述电极（25,26,27）上形成自对准硅化物层（18）和金属布线; 从而降低寄生电阻分量。

公开(公告)号：KR1020120047379A

公开(公告)日：2012-05-14

申请号：KR1020100108683

申请日：2010-11-03

Applicant: 한국전자통신연구원

Inventor： 윤석주 ,  이희동 ,  김귀동 ,  권종기

IPC: H03L7/197 ,  G06F1/04

CPC classification number: H03L7/1976 ,  H03L7/0891

Abstract: PURPOSE: A spread spectrum clock generator is provided to generate a spreading spectrum clock by controlling a division ratio using a digital signal. CONSTITUTION: A phase detector(110) receives a reference frequency signal and a frequency division signal. The phase detector detects the phase difference of the reference frequency signal and the frequency division signal. A charge pump(120) generates an electric charge or a current in response to the output of the phase detector. A loop filter(130) includes a capacitor. A voltage control oscillator(140) generates an oscillation signal corresponding to the output voltage of the loop filter. A main divider(150) receives the oscillation signal from the voltage control oscillator. The main divider divides the oscillation signal according to a certain division ratio. A division ratio controller(170) comprises a triangle wave generator(172), a delta-sigma modulator(174), a sub divider(176), and a summer(178).

Abstract translation: 目的：提供扩频时钟发生器，通过使用数字信号控制分频比来产生扩展频谱时钟。 构成：相位检测器（110）接收参考频率信号和分频信号。 相位检测器检测参考频率信号和分频信号的相位差。 电荷泵（120）响应于相位检测器的输出产生电荷或电流。 环路滤波器（130）包括电容器。 电压控制振荡器（140）产生对应于环路滤波器的输出电压的振荡信号。 主分压器（150）从压控振荡器接收振荡信号。 主分压器根据一定的分频比划分振荡信号。 分频比控制器（170）包括三角波发生器（172），Δ-Σ调制器（174），子分频器（176）和加法器（178）。

公开(公告)号：KR1020120025660A

公开(公告)日：2012-03-16

申请号：KR1020100087630

申请日：2010-09-07

Applicant: 한국전자통신연구원

Inventor： 이희동 ,  윤석주 ,  김귀동 ,  권종기 ,  조상현

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/083 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187

Abstract: PURPOSE: A phase locked loop circuit including an automatic frequency control circuit and an operating method thereof are provided to reduce time for fixing a arbitrary output frequency by including an automatic frequency control circuit which performs fast operation. CONSTITUTION: A phase detector(110) detects the phase or frequency difference of a divided oscillation signal and a reference frequency signal. A charge pump(120) generates an electric charge or current in response to the output of the phase detector. A loop filter(130) includes a capacitor. The capacitor of the loop filter is charged or discharged according to the output of the charge pump. A voltage control oscillator(140) generates an oscillation signal having a frequency corresponding to an output voltage in response to the output voltage of the loop filter. A divider(150) lowers the frequency of the oscillation signal outputted from the voltage control oscillator as much as a division ratio. An automatic frequency control circuit(160) outputs at least one or more digital code bits.

Abstract translation: 目的：提供一种包括自动频率控制电路及其操作方法的锁相环电路，通过包括执行快速操作的自动频率控制电路来减少固定任意输出频率的时间。 构成：相位检测器（110）检测分频振荡信号和基准频率信号的相位或频率差。 电荷泵（120）响应于相位检测器的输出产生电荷或电流。 环路滤波器（130）包括电容器。 环路滤波器的电容器根据电荷泵的输出进行充放电。 电压控制振荡器（140）响应于环路滤波器的输出电压产生具有对应于输出电压的频率的振荡信号。 分压器（150）将从压控振荡器输出的振荡信号的频率降低到分频比。 自动频率控制电路（160）输出至少一个或多个数字码位。