公开(公告)号：KR1020140085139A

公开(公告)日：2014-07-07

申请号：KR1020120155367

申请日：2012-12-27

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  홍경국 ,  이종석 ,  천대환

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66068 ,  H01L29/1608

Abstract: According to an embodiment of the present invention, a semiconductor device comprises an n-type epitaxial layer, a p-type epitaxial layer, and an n+ region which are disposed on a first surface of an n+ type silicon carbide substrate in order; a trench including a first portion with a linear profile and a second portion with a U shape which passes through the n+ region and the p-type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p-type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate. The second portion of the trench is disposed under the first portion of the trench. The width of the first portion of the trench is wider than the width of the second portion of the trench.

Abstract translation: 根据本发明的实施例，半导体器件包括依次设置在n +型碳化硅衬底的第一表面上的n型外延层，p型外延层和n +区域; 包括具有线性轮廓的第一部分和穿过所述n +区域和所述p型外延层的U形的第二部分的沟槽; 设置在所述沟槽内的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 设置在栅电极上的氧化膜; 设置在p型外延层上的源电极，n +区和氧化膜; 以及设置在n +型碳化硅衬底的第二表面上的漏电极。 沟槽的第二部分设置在沟槽的第一部分之下。 沟槽的第一部分的宽度比沟槽的第二部分的宽度宽。

公开(公告)号：KR1020140062868A

公开(公告)日：2014-05-26

申请号：KR1020120129748

申请日：2012-11-15

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국 ,  천대환 ,  정영균

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265

CPC classification number: H01L29/66068 ,  H01L29/086 ,  H01L29/4236

Abstract: A semiconductor device according to an embodiment of the present invention comprises: an n-type buffer layer located on a first surface of an n+ type silicon carbide substrate; a first n-type epitaxial layer located on the n-type buffer layer; a second n-type epitaxial layer located on the first n-type epitaxial layer; a first trench and a second trench which are located on the first n-type epitaxial layer and the second n-type epitaxial layer; a p+ region which is extended from the lower part of the first trench to the inside of the sidewall of the first trench; an n+ region located on the second n-type epitaxial layer; a gate insulation film located in the second trench; a gate electrode located on the gate insulation film; an oxide film located on the gate electrode; a source electrode located on the n+ region, the oxide film and the p+ region; and a drain electrode located on a second surface of the n+ type silicon carbide substrate, wherein a doping concentration of the first n-type epitaxial layer is greater than a doping concentration of the second n-type epitaxial layer, the second n-type epitaxial layer is located on each of both sides of the second trench, and a channel is arranged on the second n-type epitaxial layer.

Abstract translation: 根据本发明实施例的半导体器件包括：位于n +型碳化硅衬底的第一表面上的n型缓冲层; 位于n型缓冲层上的第一n型外延层; 位于第一n型外延层上的第二n型外延层; 位于第一n型外延层和第二n型外延层上的第一沟槽和第二沟槽; p +区，其从第一沟槽的下部延伸到第一沟槽的侧壁的内部; 位于第二n型外延层上的n +区; 位于所述第二沟槽中的栅极绝缘膜; 位于栅极绝缘膜上的栅电极; 位于栅电极上的氧化膜; 位于n +区上的源极，氧化膜和p +区; 以及位于所述n +型碳化硅衬底的第二表面上的漏电极，其中所述第一n型外延层的掺杂浓度大于所述第二n型外延层的掺杂浓度，所述第二n型外延层 层位于第二沟槽的两侧中的每一侧上，并且沟道布置在第二n型外延层上。