公开(公告)号：WO1997038492A1

公开(公告)日：1997-10-16

申请号：PCT/US1997006964

申请日：1997-04-02

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ASHE, James, J. ,  BOWERS, Derek, F. ,  McHUGH, Leo, P.

IPC: H03K19/0175

CPC classification number: H03K19/09425 ,  H03M1/785

Abstract: A three state logic input recognizes three logic levels: an intermediate level in addition to the conventional "high" and "low" levels employed by binary logic systems. The three state device may be used in purely ternary logic systems or in "hybrid" systems which combine binary and ternary logic. In a preferred embodiment, the new three state logic device (10) comprises a "passive driver" (12) which is connected to produce one of three predetermined logic levels in corresponding to impedance paths from its input terminal (16) through an external circuit to a positive or negative voltage supply. In hybrid ternary/binary applications, the new three state input device includes a decoder (14) that is connected to decode the three predetermined logic levels provided by the passive driver into binary logic for use by associated binary logic devices. In a digital-to-analog converter (DAC) (50) application, the three state input device is employed to recognize both a binary logic and a control signal at one input pin to the DAC.

Abstract translation: 三态逻辑输入识别三个逻辑电平：除二进制逻辑系统采用的常规“高”和“低”电平以外的中间电平。 三状态设备可以用于组合二进制和三元逻辑的纯三元逻辑系统或“混合”系统中。 在一个优选实施例中，新的三状态逻辑器件（10）包括一个“无源驱动器”（12），其被连接以产生三个预定逻辑电平中的一个，对应于来自其输入端（16）的外部电路的阻抗路径 到正或负电压源。 在混合三进制/二进制应用中，新的三状态输入设备包括一个解码器（14），它被连接以解码被无源驱动器提供的三个预定的逻辑电平为二进制逻辑，供相关的二进制逻辑器件使用。 在数模转换器（DAC）（50）应用中，三态输入装置用于在DAC的一个输入引脚处识别二进制逻辑和控制信号。

公开(公告)号：WO1997034390A1

公开(公告)日：1997-09-18

申请号：PCT/US1997003906

申请日：1997-03-13

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  RUCH, Jacques, G. ,  RIBNER, David, B.

IPC: H04L05/14

CPC classification number: H04H20/81 ,  H04L5/023 ,  H04L5/143

Abstract: A duplex modulation method including the steps of using a first modulation technique to send downstream information over a cable and within a first region of the signal frequency spectrum; and using a multicarrier modulation technique to send upstream information over the cable and within a second region of the frequency spectrum, wherein the first region of the signal frequency spectrum is above the second region of the signal frequency spectrum, wherein the first modulation technique is different from the multicarrier modulation technique.

Abstract translation: 一种双工调制方法，包括以下步骤：使用第一调制技术通过电缆并在信号频谱的第一区域内发送下行信息; 以及使用多载波调制技术通过所述电缆并在所述频谱的第二区域内发送上行信息，其中所述信号频谱的所述第一区域高于所述信号频谱的第二区域，其中所述第一调制技术是不同的 从多载波调制技术。

公开(公告)号：WO1997022180A1

公开(公告)日：1997-06-19

申请号：PCT/US1996019533

申请日：1996-12-09

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  TICE, Thomas, E. ,  CROOK, David, T. ,  KATTMANN, Kevin, M. ,  LANE, Charles, D.

IPC: H03K05/153

CPC classification number: H03M1/129 ,  H03M1/145

Abstract: A protection circuit inhibits saturation and damage of sensitive circuit elements (54) when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector (52) which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit (62, 64) substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multi-step/subranging analog-to-digital/converters.

Abstract translation: 当输入信号超出额定输入范围时，保护电路抑制敏感电路元件（54）的饱和和损坏。 保护电路包括超出范围检测器（52），其将输入信号与参考电平进行比较以确定其是否在该范围内。 如果不是，则控制电路（62,64）代替略微超出范围但不超出范围的补充信号，以引起任何实质的饱和。 补充信号源产生稍微超出范围的高端和低端的补充信号，误差范围不大于约750mV，处于范围之外; 超范围输入由具有最接近的值的补充信号代替。 本发明特别适用于模数/转换器的多级/次级。

公开(公告)号：WO1997014099A1

公开(公告)日：1997-04-17

申请号：PCT/US1996016209

申请日：1996-10-10

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  POTTS, James, F. ,  LEARY, Kevin, W.

IPC: G06F12/08

CPC classification number: G06F9/30047 ,  G06F12/0888

Abstract: A digital signal processor includes a control circuit for controlling transfer of instructions to and between a computation unit, a memory and an instruction cache. The memory includes a plurality of memory blocks. The control circuit includes a circuit for detecting a memory conflict condition when an instruction address on a first bus and a data address on a second bus both reference locations in one of the memory blocks in a single clock cycle. In response to the memory conflict condition, the instruction corresponding to the instruction address is fetched from the instruction cache when the instruction is stored in the instruction cache. When the instruction is not stored in the instruction cache, the instruction is fetched from memory and is loaded into the instruction cache. An internal memory conflict occurs when the instruction address and the data address reference locations in the same block of internal memory in the same clock cycle. An external memory conflict occurs when the instruction address and the data address reference locations in external memory in the same clock cycle. By selectively caching only those instructions which produce a conflict, a small instruction cache can be used.

Abstract translation: 数字信号处理器包括用于控制向计算单元，存储器和指令高速缓存之间传递指令的控制电路。 存储器包括多个存储器块。 控制电路包括用于在第一总线上的指令地址和第二总线上的数据地址两个参考位置在一个时钟周期中的一个存储器块中检测存储器冲突条件的电路。 响应于存储器冲突条件，当指令存储在指令高速缓存中时，从指令高速缓冲存储器取出与指令地址相对应的指令。 当指令不存储在指令高速缓存中时，指令从存储器中取出并加载到指令高速缓存中。 内部存储器冲突发生在指令地址和数据地址参考位置在相同的内部存储器块在相同的时钟周期。 当外部存储器中的指令地址和数据地址在同一时钟周期内引用时，会发生外部存储器冲突。 通过选择性地高速缓存产生冲突的指令，可以使用小指令高速缓存。

公开(公告)号：WO1997011522A1

公开(公告)日：1997-03-27

申请号：PCT/US1996014455

申请日：1996-09-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GOEL, Rakesh

IPC: H02P01/04

CPC classification number: H02P6/06 ,  H02P6/14 ,  H02P6/17 ,  H02P6/182

Abstract: A control system for a permanent magnet synchronous motor (12) includes a position estimator (20) for cross-correlating the back EMF of an unenergized winding (14, 16, 18) with a reference waveform to determine the estimated position of a rotor for determining rotor angle position error; an error integrator circuit (24), responsive to the rotor angle position error, for determining the angular speed of the field; an angle generator (22), responsive to the angular speed of the field, for generating the field angle position; and a waveform generator (26), responsive to the rotor angle position, for generating a periodic signal corresponding to each winding and designating a segment of that signal for driving that winding to adjust the field speed to the rotor speed.

Abstract translation: 用于永磁同步电动机（12）的控制系统包括用于将未通电绕组（14,16,18）的反电动势与参考波形互相关的位置估计器（20），以确定用于 确定转子角位置误差; 响应于转子角位置误差的误差积分器电路（24），用于确定场的角速度; 角度发生器（22），其响应于所述场的角速度，用于产生所述场角位置; 以及响应于转子角度位置的波形发生器（26），用于产生对应于每个绕组的周期性信号，并指定该信号的一段以驱动该绕组以将该转速调整到转子速度。

公开(公告)号：WO1996037765A1

公开(公告)日：1996-11-28

申请号：PCT/US1996002075

申请日：1996-02-16

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MALONE, Robert ,  JOHNSON, Brian ,  BEUCLER, Brian ,  O'REILLY, Robert ,  BOUCHER, Norman ,  OURFALIAN, Sarkis

IPC: G01M07/06

CPC classification number: G01P21/00 ,  G01M7/06

Abstract: An automatic and integrated mechanical and electrical accelerometer test system (10) includes a test fixture (12) for holding the accelerometers to be mechanically and electrically tested. A handler subsystem (16) automatically feeds the accelerometers (18, 20, 22) to the test fixture. A shaker subsystem (14) linked to the test fixture automatically vibrates the test fixture. A tester (30) electrically tests the accelerometers while the accelerometers are vibrating.

Abstract translation: 自动和集成的机械和电加速度计测试系统（10）包括用于保持加速度计被机械和电气测试的测试夹具（12）。 处理器子系统（16）自动将加速度计（18,20,22）馈送到测试夹具。 连接到测试夹具的振动子系统（14）自动振动测试夹具。 测试器（30）在加速度计振动时对加速度计进行电测试。

公开(公告)号：WO1996028892A1

公开(公告)日：1996-09-19

申请号：PCT/US1996002784

申请日：1996-02-27

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WILSON, James ,  CELLINI, Ronald, A. ,  SOBIL, James, M.

IPC: H03M03/02

CPC classification number: H03M3/372 ,  H03M3/50

Abstract: A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal. A modulator sample rate control circuit, coupled to the modulator, receives a frequency select signal representing the preselected input sample rate, and produces the noise-shaped clock signal for controlling operation of the modulator at the oversampling rate. The control circuit preferably includes a first sigma-delta modulator that sigma-delta modulates the frequency select signal. The oversampling modulator preferably includes a second sigma-delta modulator.

Abstract translation: 提供了使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。 该方法和装置包括时基的Σ-Δ调制，使得由非均匀采样产生的误差被频率形成为通过常规滤波技术降低的高频区域。 在一个实施例中，过采样调制器接收数字输入样本，并响应于噪声形状的时钟信号，调制数字输入样本以过采样率产生调制样本。 过采样率优选等于过采样比乘以预选输入采样率。 耦合到调制器的DAC将调制样本转换为模拟信号。 耦合到调制器的调制器采样率控制电路接收表示预选输入采样率的频率选择信号，并产生用于以过采样速率控制调制器的操作的噪声形状的时钟信号。 控制电路优选地包括Σ-Δ调制频率选择信号的第一Σ-Δ调制器。 过采样调制器优选地包括第二Σ-Δ调制器。

公开(公告)号：WO1996021271A1

公开(公告)日：1996-07-11

申请号：PCT/US1995014088

申请日：1995-11-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  TICE, Thomas, E. ,  CROOK, David, T. ,  KATTMAN, Kevin, M. ,  LANE, Charles, D.

IPC: H03F03/45

CPC classification number: H03F3/45098 ,  H03F1/083 ,  H03F3/45085 ,  H03F2203/45392 ,  H03F2203/45702 ,  H03F2203/45722 ,  H03F2203/5003 ,  H03M1/16

Abstract: Open-loop differential amplifiers (120, 140) are disclosed which have accurate and stable gain. The gain of these amplifiers is substantially insensitive to the effects of small-signal emitter resistance re, current gain beta and Early voltage VA. Thus, their gain can be accurately set by resistance ratios which makes them particularly useful in integrated circuits. These advantages are obtained with an output differential pair (67) that has cross-coupled base and collector terminals. In addition, resistors (141, 143, 148, 150) and a current source (146) associated with this differential pair are related to like elements (27, 28, 24, 25 and 26) that are associated with an input differential pair (21) by disclosed numerical ratios, e.g., the nominal gain G of the amplifier. Versions of the amplifiers can be adapted for use as a residue amplifier (162) in a subranging A/D converter (160).

Abstract translation: 公开了具有准确和稳定增益的开环差分放大器（120,140）。 这些放大器的增益对小信号发射极电阻re，电流增益β和早期电压VA的影响基本不敏感。 因此，它们的增益可以通过电阻比来精确地设定，这使得它们在集成电路中特别有用。 这些优点通过具有交叉耦合的基极和集电极端子的输出差分对（67）获得。 另外，与该差分对相关联的电阻（141,143,148,150）和电流源（146）与与输入差分对相关联的相似元件（27,28,24,25和26）有关， 21）通过公开的数值比例，例如放大器的标称增益G。 放大器的版本可以适用于亚排A / D转换器（160）中的残留放大器（162）。

公开(公告)号：WO1996017436A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015287

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURDEN, Frank

IPC: H03M01/44

CPC classification number: H03F3/45596 ,  H03F3/26 ,  H03F3/45085 ,  H03F2203/45612 ,  H03M1/445

Abstract: A differential amplifier operating as a magnitude amplifier may be used in a serial-type A/D converter. The differential amplifier uses complementary differential emitter pairs for folding and aligning a differential input signal. The differential input signal has a first signal and a second signal each of which is fed to one of two input circuits. One input circuit includes a bipolar npn transistor and a current sink and the other includes a bipolar pnp transistor and a current source. The outputs of the input npn transistors feed a differential pair of output pnp transistors. The emitters of the output pnp transistors are coupled, with the signal on the emitters following the lower of the differential input signals. The outputs of the input pnp transistors feed a differential pair of output npn transistors. The emitters of the output npn transistors also are coupled, with the signal on the emitters following the inputs in a predetermined manner. The results are folded signals at the outputs of the output transistors that are aligned by offset circuits.

Abstract translation: 作为幅度放大器工作的差分放大器可用于串行型A / D转换器。 差分放大器使用互补差分发射器对来折叠和对准差分输入信号。 差分输入信号具有第一信号和第二信号，每个信号被馈送到两个输入电路之一。 一个输入电路包括双极性npn晶体管和电流吸收器，另一个包括双极pnp晶体管和电流源。 输入npn晶体管的输出馈送输出pnp晶体管的差分对。 输出pnp晶体管的发射极被耦合，发射极上的信号跟随差分输入信号的较低者。 输入pnp晶体管的输出馈送差分输出npn晶体管对。 输出npn晶体管的发射极也被耦合，发射器上的信号以预定的方式跟随输入。 结果是在由偏移电路对准的输出晶体管的输出处的折叠信号。

公开(公告)号：WO1996017253A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015466

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  HOWE, Roger, T. ,  BARBER, H., Jerome ,  JUDY, Michael

IPC: G01P15/08

CPC classification number: B81B3/0008 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  Y10S73/01

Abstract: An electro-mechanical micromachined structure uses bumpers (52) to prevent contact between structures at different potentials. A beam (22) is connected to one or more anchors (26) by flexible suspensions (24), which permit the beam (22) to move along a predetermined axis relative to one or more plates (34, 36). The suspension (24) includes at least one bumper (52) positioned so that the bumper (52) will contact another part of the suspension (24) before the beam (22) contacts the plates. The bumper is made from the same material as the suspension (24), during the same processing step. The bumper (52) is positioned to take advantage of shrinkage or expansion of the beam (22) during processing which forces the bumper (52) closer to its contact point than would otherwise be possible.

Abstract translation: 机电微加工结构使用缓冲器（52）来防止在不同电位下的结构之间的接触。 梁（22）通过柔性悬架（24）连接到一个或多个锚固件（26），这允许梁（22）相对于一个或多个板（34,36）沿着预定轴线移动。 悬架（24）包括至少一个缓冲器（52），其被定位成使得缓冲器（52）在梁（22）接触板之前将接触悬架（24）的另一部分。 在相同的加工步骤中，保险杠由与悬架（24）相同的材料制成。 保险杠（52）被定位成在处理期间利用梁（22）的收缩或膨胀，这迫使保险杠（52）比其它方式更接近接触点。