公开(公告)号：US20160217311A1

公开(公告)日：2016-07-28

申请号：US15090474

申请日：2016-04-04

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Jun Zhai

IPC: G06K9/00

CPC classification number: G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

Abstract translation: 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US20160172261A1

公开(公告)日：2016-06-16

申请号：US15050110

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

公开(公告)号：US09331058B2

公开(公告)日：2016-05-03

申请号：US14097491

申请日：2013-12-05

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: H05K7/20 ,  H01L25/16 ,  H01L23/13 ,  H01L23/367 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US20160061677A1

公开(公告)日：2016-03-03

申请号：US14517387

申请日：2014-10-17

Applicant: Apple Inc.

Inventor： Caleb C. Han ,  Tongbi Jiang ,  Jun Zhai

IPC: G01L7/08

CPC classification number: G01L7/08 ,  B81B7/0048 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C2203/0792 ,  G01L9/0045 ,  G01L9/0048 ,  G01L19/0618 ,  G01L19/146 ,  G01L19/148 ,  H01L41/094 ,  H01L41/1136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48095 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/16195

Abstract: Sensor packages and manners of formation are described. In an embodiment, a sensor package includes a supporting die characterized by a recess area and a support anchor protruding above the recess area. A sensor die is bonded to the support anchor such that an air gap exists between the sensor die and the recess area. The sensor die includes a sensor positioned directly above the air gap.

Abstract translation: 描述传感器封装和形成方式。 在一个实施例中，传感器封装包括支撑模具，其特征在于凹部区域和在凹部区域上方突出的支撑锚固件。 传感器模具结合到支撑锚定件，使得在传感器模具和凹部区域之间存在气隙。 传感器模具包括位于空气间隙正上方的传感器。

公开(公告)号：US09263426B2

公开(公告)日：2016-02-16

申请号：US14593317

申请日：2015-01-09

Applicant: Apple Inc.

Inventor： Jie-Hua Zhao ,  Yizhang Yang ,  Jun Zhai ,  Chih-Ming Chung

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y02P80/30 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

公开(公告)号：US20160013156A1

公开(公告)日：2016-01-14

申请号：US14541228

申请日：2014-11-14

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Chonghua Zhong

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

公开(公告)号：US09236355B2

公开(公告)日：2016-01-12

申请号：US14331363

申请日：2014-07-15

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Mengzhi Pang ,  Se Young Yang ,  Leland W. Lew

IPC: H01L23/60 ,  H01L23/538 ,  H01L23/485 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2224/81

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.

Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 第一衬底可以包括电连接组件的第一组电导体。 在一些实施例中，组件可以包括耦合到第一衬底的至少一个电导体，使得电导体中的至少一个暴露于半导体器件封装组件的周边表面。 在一些实施例中，组件可以包括使用第二组电导体电连接到第一衬底的第二表面的第一裸片。 组件可以包括耦合到第一管芯的电子存储器模块。 在一些实施例中，组件可以包括施加到组件的上表面并且电耦合到暴露的电导体中的至少一个的屏蔽。 在使用过程中，屏蔽可能会阻碍电磁干扰。

公开(公告)号：US20150380392A1

公开(公告)日：2015-12-31

申请号：US14317799

申请日：2014-06-27

Applicant: Apple Inc.

Inventor： Mengzhi Pang ,  Jun Zhai

IPC: H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L21/568 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/81

Abstract: A semiconductor device package includes a logic die coupled to a memory die in a face-to-face configuration with small interconnect pitch (at most about 50 μm) and small distances between the die (at most about 50 μm). The logic die may be connected to a redistribution layer with terminals that are fanned out, or spaced out, to provide space for the face-to-face connections to the memory die. The memory die may be connected to the logic die before or after the logic die is connected to the redistribution layer. The logic die and the memory die may be at least partially encapsulated in an encapsulant. Routing in the redistribution layer may connect the logic die and/or the memory die to ball grid array terminals coupled to the bottom of the redistribution layer and/or discrete devices coupled to the redistribution layer.

Abstract translation: 半导体器件封装包括以小的互连间距（至多约50μm）和管芯之间的距离（至多约50μm）以面对面配置耦合到存储器管芯的逻辑管芯。 逻辑管芯可以连接到再分配层，其中端子被扇形出或间隔开，以提供用于与存储管芯的面对面连接的空间。 在逻辑管芯连接到再分配层之前或之后，存储器管芯可以连接到逻辑管芯。 逻辑管芯和存储器管芯可以至少部分地封装在密封剂中。 再分配层中的路由可以将逻辑管芯和/或存储器管芯连接到耦合到再分配层的底部的耦合到再分配层的离散器件的球栅阵列终端。

公开(公告)号：US20150171063A1

公开(公告)日：2015-06-18

申请号：US14192145

申请日：2014-02-27

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Yizhang Yang ,  Mengzhi Pang

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/165 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die electrically connected to the first substrate such that the first die is directly bonded to the first substrate. The semiconductor device package assembly may include a second substrate directly bonded to a surface of the first die. The semiconductor device package assembly may include an electronic memory module. The electronic memory module may be directly bonded to the second substrate. The semiconductor device package assembly may include a thermally conductive material directly applied to the electronic memory module. The semiconductor device package assembly may include a heat spreader directly bonded to the thermally conductive material. The heat spreader may function to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side.

Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 半导体器件封装组件可以包括电连接到第一衬底的第一裸片，使得第一裸片直接结合到第一衬底。 半导体器件封装组件可以包括直接接合到第一管芯的表面的第二衬底。 半导体器件封装组件可以包括电子存储器模块。 电子存储器模块可以直接结合到第二衬底。 半导体器件封装组件可以包括直接施加到电子存储器模块的导热材料。 半导体器件封装组件可以包括直接结合到导热材料的散热器。 散热器可以起到将热量从第一模具和电子存储器模块通过散热器从第一侧传递到第二侧的功能。

公开(公告)号：US20140210106A1

公开(公告)日：2014-07-31

申请号：US13753014

申请日：2013-01-29

Applicant: APPLE INC.

Inventor： Jun Zhai

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13124 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. The bottom package includes a die coupled to an interposer layer with an adhesive layer. One or more terminals are coupled to the interposer layer on the periphery of the die. The terminals and the die are at least partially encapsulated in an encapsulant. The terminals and the die are coupled to a redistribution layer (RDL). Terminals on the bottom of the RDL are used to couple the PoP package to a motherboard or a printed circuit board (PCB). One or more additional terminals couple the interposer layer to the top package. The additional terminals may be located anywhere along the surface of the interposer layer.

Abstract translation: PoP（封装封装）封装包括一个耦合到顶部封装的底部封装。 底部包装包括连接到具有粘合剂层的插入层的裸片。 一个或多个端子耦合到管芯外围上的插入层。 端子和管芯至少部分地封装在密封剂中。 端子和管芯耦合到再分配层（RDL）。 RDL底部的端子用于将PoP封装耦合到主板或印刷电路板（PCB）。 一个或多个附加端子将插入层耦合到顶部封装。 附加端子可以位于沿着插入层的表面的任何位置。