公开(公告)号：WO2006055821A3

公开(公告)日：2006-08-24

申请号：PCT/US2005041922

申请日：2005-11-18

Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  LEE KYEONGHO

Inventor： PARK JOONBAE ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  LEE KYEONGHO

IPC: H04B1/04

CPC classification number: H04B1/26

Abstract: A wireless receiver and a wireless receiving method are provided wherein a frequency of a radio frequency (RF) is down-converted into a frequency of a substantially zero intermediate frequency (IF) signal or a substantially low IF signal. The down-converted signal may be filtered by an integrated filter having a low quality factor and then up-converted again into a particular IF signal, thereby integrating an external element. For example, a receiving device may receive a RF signal in a required band. A frequency down-converting device may down-convert a frequency so that a center frequency of the RF signal becomes zero. A channel select filtering device may select a required channel from the signals whose frequency is down-converted. An IF signal converting device may up-convert a frequency of the channel selected signal into a required IF. An IF processing device may extract a baseband signal after the converted IF signal is inputted and processed. An amplifying device may amplify a signal with a gain required in a process of converting a frequency.

Abstract translation: 提供了一种无线接收机和无线接收方法，其中射频（RF）的频率被下变频成基本为零的中频（IF）信号或基本上低的IF信号的频率。 下变频信号可以由具有低质量因子的积分滤波器滤波，然后再次上变频成特定的IF信号，从而整合外部元件。 例如，接收设备可以接收所需频带中的RF信号。 降频转换装置可以降频转换频率，使得RF信号的中心频率变为零。 频道选择滤波装置可以从频率被下变频的信号中选择所需频道。 IF信号转换装置可以将频道选择信号的频率上变频成所需的IF。 IF处理装置可以在转换的IF信号被输入和处理之后提取基带信号。 放大装置可以放大具有在转换频率的过程中所需的增益的信号。

公开(公告)号：WO2005022598A3

公开(公告)日：2005-10-06

申请号：PCT/US2004027800

申请日：2004-08-27

Applicant: GCT SEMICONDUCTOR INC ,  KOO YIDO ,  HUH HYUNGKI ,  LEE KANG YOON ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

Inventor： KOO YIDO ,  HUH HYUNGKI ,  LEE KANG YOON ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC: H01L23/64 ,  H01L29/00

CPC classification number: H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Abstract translation: 集成电路封装包括由接合线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的键合焊盘连接至封装的I / O引脚的第一导线和将相同键合焊盘连接至相同引脚的第二导线形成。 通过在集成电路封装的范围内形成电感器环路，实现了对空间要求的实质性减少，这反过来又促进了小型化。

公开(公告)号：WO2005022933A3

公开(公告)日：2005-08-11

申请号：PCT/US2004027799

申请日：2004-08-27

Applicant: GCT SEMICONDUCTOR INC ,  JEON YOUNG-DEUK ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

Inventor： JEON YOUNG-DEUK ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC: H04B1/38

CPC classification number: H04B1/1027 ,  H03H11/1252 ,  H03H11/1291 ,  H03J1/0008 ,  H04B1/44

Abstract: A system and method for filtering signals in a communications system reduces hardware and chip size requirements by selectively connecting a filter along transmitter and receiver paths of a transceiver. In operation, a controller generated signals for connecting the filter along the transmitter path when the transceiver is in transmitter mode and for connecting the filter along the receiver path when the transmitter is in receiver mode. The controller then generates additional signals for setting one or more parameters of the filter based on the path connected, or put differently based on the operational mode of the transceiver. In a variation, the controller sets the parameters of additional elements coupled to the filter as a way of further controlling processing of the transmitter and receiver signals.

Abstract translation: 用于对通信系统中的信号进行滤波的系统和方法通过沿收发器的发射机和接收机路径选择性地连接滤波器来降低硬件和芯片尺寸的要求。 在操作中，当收发器处于发射机模式时，控制器产生用于沿着发射机路径连接滤波器的信号，并且当发射机处于接收机模式时，控制器沿着接收机路径连接滤波器。 然后，控制器产生附加信号，用于基于连接的路径设置滤波器的一个或多个参数，或者基于收发器的操作模式进行不同的设置。 在一个变型中，控制器设置耦合到滤波器的附加元件的参数作为进一步控制发射机和接收机信号的处理的一种方式。

公开(公告)号：WO2004040822A3

公开(公告)日：2004-07-08

申请号：PCT/US0333708

申请日：2003-10-23

Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE KYEONGHO ,  SONG EUNSEOK ,  JUNG YEONJAE

Inventor： PARK JOONBAE ,  LEE KYEONGHO ,  SONG EUNSEOK ,  JUNG YEONJAE

IPC: H04B1/10 ,  H04L25/10

CPC classification number: H04B1/109

Abstract: A communications receiver includes a baseband signal recovery circuit (4) which uses a low-IF architecture for data reception. The baseband signal recovery circuit uses a full-analog implementation for channel selection and filtering (5). Thus, the overhead placed on the design of analog-to-digital converter is greatly relaxed and most of hardware can be re-used for multi-mode applications with only a slight modification.

Abstract translation: 通信接收机包括使用低IF架构进行数据接收的基带信号恢复电路（4）。 基带信号恢复电路使用全模拟实现进行信道选择和滤波（5）。 因此，放置在模数转换器设计上的开销大大放松，大多数硬件可以重新用于多模式应用，只需稍作修改。

公开(公告)号：EP1228564A4

公开(公告)日：2007-01-24

申请号：EP00978551

申请日：2000-11-13

Applicant: GCT SEMICONDUCTOR INC

Inventor： LEE KYEONGHO ,  JEONG DEOG-KYOON ,  PARK JOONBAE ,  KIM WONCHAN

IPC: H03H11/22 ,  H03L7/089 ,  H03L7/099 ,  H03L7/197 ,  H04B1/28 ,  H03K3/00

CPC classification number: H03L7/0995 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03L7/0891 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

公开(公告)号：EP1514351A4

公开(公告)日：2005-12-07

申请号：EP03728954

申请日：2003-06-05

Applicant: GCT SEMICONDUCTOR INC

Inventor： KOO YIDO ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC: H03B5/08 ,  H03B1/00 ,  H03B5/12 ,  H03L7/099 ,  H03L7/08

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H03B2201/025 ,  H03J2200/10

Abstract: A voltage-controlled oscillator (600) including an active oscillator circuit (610), an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator (600). Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit (610). To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors (622). The resistors can be configured in several different ways so that the voltage-controlled oscillator (600) can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

Abstract translation: 公开了一种包括有源振荡器电路，电感器和电容电路的压控振荡器。 电容电路选择性地导通和截止以控制压控振荡器的频率。 特别地，电容电路中的电感器和电容器形成LC电路，从而向有源振荡器电路提供反馈。 为了避免损坏电容电路中的开关，电容电路还包括电阻器。 电阻器可以以多种不同的方式进行配置，使得压控振荡器具有高可靠性，以及具有恒定相位噪声性能的宽调谐范围。

公开(公告)号：EP1803216A4

公开(公告)日：2008-12-10

申请号：EP05802909

申请日：2005-09-21

Applicant: GCT SEMICONDUCTOR INC

Inventor： KOO YIDO ,  AHN YOUNGHO ,  SONG EUNSEOK ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC: H03D3/24

CPC classification number: H03L7/0895 ,  H03L7/1976

Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PDF to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

公开(公告)号：EP1803186A4

公开(公告)日：2008-09-24

申请号：EP05800772

申请日：2005-09-21

Applicant: GCT SEMICONDUCTOR INC

Inventor： PARK JOONBAE ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  LEE KYEONGHO

IPC: H01P5/12 ,  H03L7/087 ,  H03L7/187

CPC classification number: H03L7/113 ,  H03L7/087 ,  H03L7/10 ,  H03L7/187

Abstract: An apparatus and method of oscillating a wideband frequency are disclosed. The apparatus includes: a frequency oscillating unit for oscillating a predetermined frequency; a phase-locked loop for comparing the oscillated frequency and a reference frequency by feedbacking the oscillated frequency from the frequency oscillating unit and fixing an oscillating frequency of the frequency oscillating unit; and a variable dividing unit for varying a division ratio to approach to a frequency band required by the oscillating frequency and dividing the oscillating frequency.

公开(公告)号：EP1556952A4

公开(公告)日：2005-12-21

申请号：EP03779214

申请日：2003-10-23

Applicant: GCT SEMICONDUCTOR INC

Inventor： AHN YOUNGHO ,  SONG EUNSEOK ,  KOO YIDO ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC: H03L7/197 ,  H03L7/06

CPC classification number: H03L7/1978

Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

Abstract translation: 用于改善频率发生器的信噪比的系统和方法抑制了由于内部发生器电路中的失配而产生的相位噪声和噪声。 这是利用调制方案实现的，该调制方案将发生器的环路带宽之外的寄生噪声信号移位。 当以这种方式移动时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全移除或以任何期望的程度移除。 在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。 在另一个实施例中，输入到锁相环中的参考信号被调制以实现噪声抑制。 在另一个实施例中，上述形式的调制被组合以实现期望的频移。 通过这些调制技术，频率发生器的信噪比可以显着提高，同时实现更快的锁定时间。

公开(公告)号：EP1371167A4

公开(公告)日：2005-07-13

申请号：EP02723501

申请日：2002-03-20

Applicant: GCT SEMICONDUCTOR INC

Inventor： HUH HYUNGKI ,  SONG EUNSEOK ,  LEE KANG YOON ,  KOO YIDO ,  LEE JEONGWOO ,  PARK JOONBAE ,  LEE KYEONGHO

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/095 ,  H03L7/197 ,  H04L7/033 ,  H04L7/00

CPC classification number: H03L7/1976 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/095

Abstract: A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.