公开(公告)号：US11567277B1

公开(公告)日：2023-01-31

申请号：US17472846

申请日：2021-09-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Mark Levy ,  Siva P. Adusumilli

IPC: G02B6/43 ,  G02B6/42

Abstract: Structures that include a distributed Bragg reflector and methods of fabricating a structure that includes a distributed Bragg reflector. The structure includes a substrate, an optical component, and a distributed Bragg reflector positioned between the optical component and the substrate. The distributed Bragg reflector includes airgaps and silicon layers that alternate in a vertical direction with the airgaps to define a plurality of periods.

公开(公告)号：US11545577B2

公开(公告)日：2023-01-03

申请号：US17114554

申请日：2020-12-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/04

Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

公开(公告)号：US20220413232A1

公开(公告)日：2022-12-29

申请号：US17362154

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Spencer Porter ,  Mark Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/42

Abstract: Structures for a coupler and methods of forming a structure for a coupler. A structure for a directional coupler may include a first waveguide core having one or more first airgaps and a second waveguide core including one or more second airgaps. The one or more second airgaps are positioned in the second waveguide core adjacent to the one or more first airgaps in the first waveguide core. A structure for an edge coupler is also provided in which the waveguide core of the edge coupler includes one or more airgaps.

公开(公告)号：US11515397B2

公开(公告)日：2022-11-29

申请号：US16934669

申请日：2020-07-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Siva P. Adusumilli ,  Vibhor Jain ,  Steven Bentley

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/06 ,  H01L21/763 ,  H01L21/8234 ,  H01L29/36

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.

公开(公告)号：US11422303B2

公开(公告)日：2022-08-23

申请号：US17108732

申请日：2020-12-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  G02B6/24

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a waveguide structure with attenuator and methods of manufacture. The structure includes: a waveguide structure including semiconductor material; an attenuator underneath the waveguide structure; an airgap structure vertically aligned with and underneath the waveguide structure and the attenuator; and shallow trench isolation structures on sides of the waveguide structure and merging with the airgap structure.

公开(公告)号：US20220155535A1

公开(公告)日：2022-05-19

申请号：US17099834

申请日：2020-11-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: G02B6/42 ,  H01L31/0256 ,  H01L31/02

Abstract: A photodetector array includes a substrate, and an array of pixels over the substrate. Each pixel includes a set of diffraction gratings directly on a semiconductor photodetector. A pitch of the set of diffraction gratings associated with each pixel in the array of pixels are different to enable each pixel to detect a specific wavelength of light different than other pixels of the array of pixels. An air cavity may be provided in the substrate under the germanium photodetector to improve light absorption. A method of forming the photodetector array is also disclosed.

公开(公告)号：US11320589B1

公开(公告)日：2022-05-03

申请号：US17084186

申请日：2020-10-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Siva P. Adusumilli ,  Bo Peng ,  Kenneth J. Giewont

IPC: G02B6/124 ,  G02B6/12 ,  G02B6/13

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgap and methods of manufacture. The structure includes: a substrate material comprising one or more airgaps; and a grating coupler disposed over the substrate material and the one or more airgaps.

公开(公告)号：US11183514B2

公开(公告)日：2021-11-23

申请号：US16561956

申请日：2019-09-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli ,  Michel J. Abou-Khalil

IPC: H01L27/092 ,  H01L27/12 ,  H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

公开(公告)号：US11152520B1

公开(公告)日：2021-10-19

申请号：US16868773

申请日：2020-05-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/0232 ,  H01L27/144 ,  H01L31/18 ,  H01L31/105 ,  H01L31/028

Abstract: A photodetector includes a photodetecting region in a semiconductor substrate, and a reflector extending at least partially along a sidewall of the photodetecting region in the semiconductor substrate. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows use of thinner germanium for the photodetecting region. The air gap may have a variety of internal features to direct electromagnetic radiation towards the photodetecting region.

公开(公告)号：US11152394B1

公开(公告)日：2021-10-19

申请号：US16992445

申请日：2020-08-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/763

Abstract: A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. The structure also includes a first active device and a second active device. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region is in the semiconductor substrate under the buried insulator layer. The polycrystalline isolation region is under the first active device, but not under the second active device. The polycrystalline isolation region extends to different depths into the semiconductor substrate. The first and second active devices may include monocrystalline active regions, and a third polycrystalline active region may also be in the SOI layer over the polycrystalline isolation region.