公开(公告)号：US11545577B2

公开(公告)日：2023-01-03

申请号：US17114554

申请日：2020-12-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/04

Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

公开(公告)号：US12278178B2

公开(公告)日：2025-04-15

申请号：US17809610

申请日：2022-06-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michael J. Hauser ,  Michael J. Zierak

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528 ,  H01L23/62

Abstract: An integrated circuit (IC) structure includes a transistor in a device layer over a substrate, the transistor including a gate; and a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer. A process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication, and the metal interconnects allow opening of the fuse element to deactivate the PID protection structure after fabrication.

公开(公告)号：US12154956B1

公开(公告)日：2024-11-26

申请号：US18632902

申请日：2024-04-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Mark D. Levy ,  John J. Ellis-Monaghan ,  Michael J. Zierak ,  Kristin Marie Welch

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.

公开(公告)号：US20230188131A1

公开(公告)日：2023-06-15

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US20220181501A1

公开(公告)日：2022-06-09

申请号：US17114554

申请日：2020-12-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

IPC: H01L29/786 ,  H01L29/04 ,  H01L21/02 ,  H01L21/8234

Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

公开(公告)号：US20250142860A1

公开(公告)日：2025-05-01

申请号：US18385255

申请日：2023-10-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven J. Bentley ,  Santosh Sharma ,  Johnatan A. Kantarovsky ,  Mark D. Levy ,  Michael J. Zierak

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a gate structure; a first barrier layer under and adjacent to the gate structure; and a second barrier layer over the first barrier layer and which is adjacent to the gate structure.

公开(公告)号：US20250120155A1

公开(公告)日：2025-04-10

申请号：US18376668

申请日：2023-10-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Johnatan A. Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Steven J. Bentley

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.

公开(公告)号：US20250089284A1

公开(公告)日：2025-03-13

申请号：US18243910

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Mark D. Levy ,  Steven J. Bentley

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778

Abstract: A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.

公开(公告)号：US12028053B2

公开(公告)日：2024-07-02

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US11972999B2

公开(公告)日：2024-04-30

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/417 ,  H01L29/732

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L29/41708 ,  H01L29/7325

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.