公开(公告)号：JP2005170787A

公开(公告)日：2005-06-30

申请号：JP2004357515

申请日：2004-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES W III ,  MITCHELL PETER H ,  NESBIT LARRY A

IPC: B82B3/00 ,  C01B31/02 ,  C30B25/02 ,  C30B29/02 ,  C30B29/60 ,  H01L29/15 ,  H01L29/786 ,  H01L51/30

CPC classification number: H01L51/0512 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/22 ,  C01B2202/34 ,  C30B25/02 ,  C30B29/02 ,  C30B29/605 ,  H01L51/0048 ,  Y10S977/854

Abstract: PROBLEM TO BE SOLVED: To provide a method for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on a plurality of synthesis sites carried by a substrate and structures formed thereby.
SOLUTION: After an initial growth stage, synthesis at synthesis sites is interrupted and specific synthesis sites bearing conducting carbon nanotubes are altered so as to halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration, so that semiconducting carbon nanotubes can be lengthened to a greater length than the conducting carbon nanotubes.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构来选择半导体碳纳米管的方法。 解决方案：在初始生长阶段之后，中断合成位点的合成，改变带有导电碳纳米管的特定合成位点，以阻止导电碳纳米管的延长。 具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004048001A

公开(公告)日：2004-02-12

申请号：JP2003183483

申请日：2003-06-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BURNHAM JAY S ,  CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  MARGARET L GIBSON ,  NAKOS JAMES S ,  SHANK STEVEN M

IPC: H01L21/318 ,  H01L21/28 ,  H01L21/314 ,  H01L21/324 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28194 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/324 ,  H01L29/4908 ,  H01L29/518 ,  H01L29/66757

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable gate insulation film with respect to a gate insulation film forming method by silicon nitride oxide. SOLUTION: The gate insulation film forming method includes a process for preparing a substrate, a process for forming a silicon dioxide layer on the top surface of the substrate, a process for exposing the silicon dioxide layer to a plasma-nitride forming process in order to change the silicon dioxide layer into a silicon nitride oxide layer, and a process for subjecting the silicon nitride oxide layer to spike-like rapid annealing. COPYRIGHT: (C)2004,JPO

公开(公告)号：JPH11274478A

公开(公告)日：1999-10-08

申请号：JP2893699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  WILLIAM H MA ,  MANDELMAN JACK A

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2255 ,  H01L29/66621 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element reducing a short channel effect. SOLUTION: An element has a trench 370 formed in a silicon substrate 305. The channel 380 of the element is formed on the bottom portion of the trench 370. Diffusion layers 310, 320 are formed adjacently to both sides of the trench 370 and are extended along the side walls of the trench 370 and under a part of the trench 370 to form diffusion extension parts 315, 325, whereby each diffusion layer is connected to each edge of the element channel.

Abstract translation: 要解决的问题：提供减少短通道效应的半导体元件。 解决方案：元件具有形成在硅衬底305中的沟槽370.元件的沟道380形成在沟槽370的底部上。扩散层310,320形成在沟槽370的两侧相邻并且延伸 沿着沟槽370的侧壁并在沟槽370的一部分之下形成扩散延伸部分315,325，由此每个扩散层连接到元件沟道的每个边缘。

公开(公告)号：JP2007227920A

公开(公告)日：2007-09-06

申请号：JP2007037510

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HORAK DAVID VACLAV ,  ETHAN HARRISON CANNON ,  FURUKAWA TOSHIHARU ,  CHARLES WILLIAM KOBURGER III ,  JIMMY KONSTANTINOS KONTOS ,  HAKEY MARK C

IPC: H01L27/08 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor and a device structure which suppress the latch-up in a bulk CMOS device.
SOLUTION: The method includes a step of forming a trench in a semiconductor material of a substrate, while the trench has a first side wall disposed between a pair of doped wells demarcated in the semiconductor material of the substrate. The method further includes a step of forming an etching mask in the trench to mask partially the basal surface of the trench, and successively a step of removing the semiconductor material of the substrate exposing in the basal surface which has been partially masked and demarcating a second side wall which deepens the trench and has been narrowed. A dielectric material is filled in the deepened trench to demarcate trench separation regions of devices constructed in the doped wells. The dielectric material filled in the extended part of the deepened trench improves the suppression of the latch-up.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造半导体的方法和抑制体CMOS器件中的闩锁的器件结构。 解决方案：该方法包括在衬底的半导体材料中形成沟槽的步骤，而沟槽具有设置在衬底的半导体材料中划分的一对掺杂阱之间的第一侧壁。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩模沟槽的基面的步骤，并且连续地去除已经被部分掩蔽并且划分第二个的基底表面中露出的衬底的半导体材料的步骤 侧壁加深了沟槽并缩小了。 将介电材料填充在加深的沟槽中以划定在掺杂阱中构造的器件的沟槽分离区域。 填充在加深沟槽的延伸部分中的电介质材料改善了闩锁的抑制。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007201463A

公开(公告)日：2007-08-09

申请号：JP2007009439

申请日：2007-01-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHARLES WILLIAM KOBURGER III ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK ALLAN

IPC: H01L27/08 ,  H01L21/265 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76237 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device adapted to reduce latchups. SOLUTION: The semiconductor device includes (1) a shallow-trench-isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second side of the STI oxide region, wherein the portions of the first and second MOSFETs are coupled into a loop to form first and second bipolar junction transistors (BJTs); and (4) a dopant-implanted region, formed below the STI oxide region, where the dopant-implanted region forms a portion of the BJT loop and is adapted to reduce a gain of the loop. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供适于减少闭锁的半导体器件。 解决方案：半导体器件包括（1）浅沟槽隔离（STI）氧化物区域; （2）耦合到所述STI氧化物区域的第一侧的第一金属氧化物半导体场效应晶体管（MOSFET）; （3）耦合到所述STI氧化物区域的第二侧的第二MOSFET，其中所述第一和第二MOSFET的所述部分耦合到环中以形成第一和第二双极结型晶体管（BJT）; 和（4）掺杂剂注入区域，其形成在STI氧化物区域下方，其中掺杂剂注入区域形成BJT环路的一部分并且适于减小环路的增益。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007129233A

公开(公告)日：2007-05-24

申请号：JP2006299228

申请日：2006-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOBURGER CHARLES W III ,  HORAK DAVID V ,  HOLMES STEVEN JOHN ,  HAKEY MARK C ,  FURUKAWA TOSHIHARU

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L29/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

Abstract: PROBLEM TO BE SOLVED: To improve a manufacturing process of a three-dimensional integrated circuit chip or a wafer assembly, and further in detail, to make it possible to process chips in an arrayed state on a wafer before arranging the chips as stack.
SOLUTION: The manufacture of the three-dimensional integrated circuit is disclosed wherein chip density can be made extremely high, and the wafer can be processed while keeping a planar form as a whole.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了改进三维集成电路芯片或晶片组件的制造工艺，并且进一步详细地，可以在将芯片布置在晶片之前以晶片的阵列状态处理芯片为 叠加。 解决方案：公开了三维集成电路的制造，其中芯片密度可以非常高，并且可以在保持平面形状作为整体的同时处理晶片。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007081361A

公开(公告)日：2007-03-29

申请号：JP2006001706

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  STEVEN J HOLMES ,  NATZLE WESLEY C

IPC: H01L21/205 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for selectively accumulating a germanium spacer on a nitride. SOLUTION: In a method for selectively forming a germanium structure in a semiconductor manufacturing process, a native oxide is removed in a chemical oxide removing (COR) process, then surfaces of heated nitride and oxide are exposed to a germanium-containing gas to selectively form the germanium only on the surface of the nitride, not on the surface of the oxide. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在氮化物上选择性地积聚锗间隔物的结构和方法。 解决方案：在半导体制造工艺中选择性地形成锗结构的方法中，在化学氧化物去除（COR）工艺中除去天然氧化物，然后将加热的氮化物和氧化物的表面暴露于含锗气体 以仅选择性地在氮化物的表面上形成锗，而不是在氧化物的表面上形成锗。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006344960A

公开(公告)日：2006-12-21

申请号：JP2006156597

申请日：2006-06-05

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  STEPHEN J HOLMES ,  HORAK DAVID V ,  MITCHELL PETER H

IPC: H01L21/027 ,  G03F7/20

Abstract: PROBLEM TO BE SOLVED: To provide an immersion lithography device and its method. SOLUTION: A lithographic optical column structure is disclosed for performing immersion lithography, at least on a projection optical system and a wafer of an optical system inside different fluids of equal pressure. In particular, a supercritical fluid is introduced to the periphery of the wafer with identical pressure, and another fluid, for example an inert gas, is introduced in at least the projection optical system of the optical system, thereby comprising the immersion lithography device which does not require special lenses. Furthermore, a chamber is provided which encloses the wafer to be exposed and at least a projection optical component of the optical system, and is filled with a supercritical immersion fluid. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JP2004128494A

公开(公告)日：2004-04-22

申请号：JP2003325279

申请日：2003-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BYONJU PAKU ,  MANDELMAN JACK A ,  FURUKAWA TOSHIHARU

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

Abstract: PROBLEM TO BE SOLVED: To provide a multi-mesa FET structure having a doped sidewall for a source/drain region and its forming method. SOLUTION: This method makes use of the fact that when using a doping method which does not depend on a geometric shape such as a vapor doping or a plasma doping, a uniform doping of the whole sidewall is obtained by exposing the source and the drain sidewall during manufacturing. As a result, a device manufactured can have a large quantity of current per unit area of a silicon because it has a threshold voltage and a current density that does not depend on the depth and controlled with accuracy, and also its mesa quantity is extremely high compared with a mesa which can be formed by a conventional technology. Instead of a normal subtractive etching method, a multi-mesa FET structure forming method using a Damascene method gate process or a Damascene method alternate gate process is included. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004056119A

公开(公告)日：2004-02-19

申请号：JP2003160554

申请日：2003-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM R

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/76237

Abstract: PROBLEM TO BE SOLVED: To improve a leakage current characteristic at or below the threshold of a trench discrete type FET element.
SOLUTION: A slot in a vertical direction is formed in an stacked structure 14 adhered to a silicon substrate 10 covered with an oxide 12, and thereafter a spacer is formed on the sidewall of the slot. Then, a trench is formed in the substrate 10 by etching. A horizontal ledge appears adjacent to the trench, on the exposed surface of the substrate covered with the oxide by removal of the spacer. The conduction of an end in the element is suppressed by injecting a proper impurity into this ledge.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提高等于或低于沟槽离散型FET元件的阈值的漏电流特性。 解决方案：垂直方向的槽形成在粘附到被氧化物12覆盖的硅衬底10上的堆叠结构14中，然后在槽的侧壁上形成间隔件。 然后，通过蚀刻在衬底10中形成沟槽。 水平凸缘出现在沟槽附近，通过移除间隔件，在被氧化物覆盖的基板的暴露表面上。 通过在该凸缘中注入适当的杂质来抑制元件中端部的导通。 版权所有（C）2004，JPO