公开(公告)号：EP1743366A4

公开(公告)日：2009-11-11

申请号：EP05746299

申请日：2005-04-21

Applicant: IBM

Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1849187A4

公开(公告)日：2010-11-17

申请号：EP06717977

申请日：2006-01-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

公开(公告)号：EP1430536A4

公开(公告)日：2006-04-26

申请号：EP02796462

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.

公开(公告)号：JP2007109632A

公开(公告)日：2007-04-26

申请号：JP2006210142

申请日：2006-08-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN JOHN ,  HORAK DAVID V ,  KOBURGER CHARLES WILLIAM III ,  PASTEL LEAH MARIE PFEIFER

IPC: H01H1/26 ,  B81B3/00 ,  G01P15/135 ,  G01R19/04 ,  H01H1/02 ,  H01H35/14 ,  H01H36/00

CPC classification number: G01P15/0802 ,  B82Y15/00 ,  G01P15/06 ,  G01P15/0891 ,  G01P15/135 ,  H01H1/0094 ,  H01H35/14

Abstract: PROBLEM TO BE SOLVED: To provide an acceleration value and voltage measuring device, as well as, a manufacturing method of the acceleration value and voltage measuring device.
SOLUTION: This acceleration value and voltage measuring device has a conductive plate on the upper face of a first insulating layer, a second insulating layer which is the second insulating layer on the upper face of the conductive plate and in which the upper face of the plate is exposed to the opening of the second insulating layer, conductive nanotubes that are bridged over the opening, and conductive contacts to the nanotubes.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供加速度值和电压测量装置，以及加速度值和电压测量装置的制造方法。 解决方案：该加速度值和电压测量装置在第一绝缘层的上表面上具有导电板，第二绝缘层是导电板的上表面上的第二绝缘层，其中上表面 暴露于第二绝缘层的开口，桥接在开口上的导电纳米管和与纳米管的导电接触。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2012145582A

公开(公告)日：2012-08-02

申请号：JP2012016866

申请日：2012-01-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN JOHN ,  HORAK DAVID V ,  KOBURGER CHARLES WILLIAM III ,  PASTEL LEAH MARIE PFEIFER

IPC: G01P15/06 ,  G01P15/135 ,  G01R15/06 ,  G01R29/12 ,  H01H35/14

CPC classification number: G01P15/0802 ,  B82Y15/00 ,  G01P15/06 ,  G01P15/0891 ,  G01P15/135 ,  H01H1/0094 ,  H01H35/14

Abstract: PROBLEM TO BE SOLVED: To provide passive maximum acceleration and voltage measurement devices which are compact and do not need a power supply.SOLUTION: A device includes an electrically conductive plate 110 on a top surface of a first insulating layer 105; a second insulating layer 130 on a top surface of the conductive plate 110; and conductive nanotubes 180 suspended across an opening 135 in the second insulating layer 130. Because of acceleration perpendicular to the surface of the conductive plate 110, the nanotubes 180 are bent to be in contact with the conductive plate 110 and held by the van der Waals force.

Abstract translation: 要解决的问题：提供紧凑型无需电源的被动最大加速度和电压测量装置。 解决方案：器件包括在第一绝缘层105的顶表面上的导电板110; 在导电板110的顶表面上的第二绝缘层130; 以及悬挂在第二绝缘层130中的开口135上的导电纳米管180.由于垂直于导电板110的表面的加速度，纳米管180弯曲成与导电板110接触并且被范德华力 力。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2006013504A

公开(公告)日：2006-01-12

申请号：JP2005182260

申请日：2005-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  MASTERS MARK E ,  MITCHELL PETER H

IPC: H01L27/10 ,  G11C11/00 ,  G11C13/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/06 ,  H01L29/786

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/17 ,  H01L27/108 ,  H01L27/10861 ,  H01L27/10873 ,  Y10S977/742

Abstract: PROBLEM TO BE SOLVED: To provide a gain cell for a memory circuit, a memory circuit comprising multiple gain cells, and a method of producing such gain cells and memory circuits. SOLUTION: A memory gain cell 64 includes a storage capacitor 38, a write device which is electrically coupled to the storage capacitor for charging and discharging the storage capacitor, and a read device. The read device includes one or more semiconducting carbon nanotubes 50 each of which is electrically coupled between a source and a drain. A portion of each semiconducting carbon nanotube is gated by a read gate 60 and the storage capacitor, thereby regulating a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于存储器电路的增益单元，包括多个增益单元的存储器电路，以及产生这种增益单元和存储器电路的方法。 存储增益单元64包括存储电容器38，电耦合到用于对存储电容器充电和放电的存储电容器的写装置和读装置。 读取装置包括一个或多个半导体碳纳米管50，每个碳纳米管电耦合在源极和漏极之间。 每个半导体碳纳米管的一部分由读门60和存储电容器门控，从而调节从源极到漏极流过每个半导体碳纳米管的电流。 电流与存储电容器存储的电荷成比例。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2007227920A

公开(公告)日：2007-09-06

申请号：JP2007037510

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HORAK DAVID VACLAV ,  ETHAN HARRISON CANNON ,  FURUKAWA TOSHIHARU ,  CHARLES WILLIAM KOBURGER III ,  JIMMY KONSTANTINOS KONTOS ,  HAKEY MARK C

IPC: H01L27/08 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor and a device structure which suppress the latch-up in a bulk CMOS device.
SOLUTION: The method includes a step of forming a trench in a semiconductor material of a substrate, while the trench has a first side wall disposed between a pair of doped wells demarcated in the semiconductor material of the substrate. The method further includes a step of forming an etching mask in the trench to mask partially the basal surface of the trench, and successively a step of removing the semiconductor material of the substrate exposing in the basal surface which has been partially masked and demarcating a second side wall which deepens the trench and has been narrowed. A dielectric material is filled in the deepened trench to demarcate trench separation regions of devices constructed in the doped wells. The dielectric material filled in the extended part of the deepened trench improves the suppression of the latch-up.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造半导体的方法和抑制体CMOS器件中的闩锁的器件结构。 解决方案：该方法包括在衬底的半导体材料中形成沟槽的步骤，而沟槽具有设置在衬底的半导体材料中划分的一对掺杂阱之间的第一侧壁。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩模沟槽的基面的步骤，并且连续地去除已经被部分掩蔽并且划分第二个的基底表面中露出的衬底的半导体材料的步骤 侧壁加深了沟槽并缩小了。 将介电材料填充在加深的沟槽中以划定在掺杂阱中构造的器件的沟槽分离区域。 填充在加深沟槽的延伸部分中的电介质材料改善了闩锁的抑制。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007129233A

公开(公告)日：2007-05-24

申请号：JP2006299228

申请日：2006-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOBURGER CHARLES W III ,  HORAK DAVID V ,  HOLMES STEVEN JOHN ,  HAKEY MARK C ,  FURUKAWA TOSHIHARU

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L29/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

Abstract: PROBLEM TO BE SOLVED: To improve a manufacturing process of a three-dimensional integrated circuit chip or a wafer assembly, and further in detail, to make it possible to process chips in an arrayed state on a wafer before arranging the chips as stack.
SOLUTION: The manufacture of the three-dimensional integrated circuit is disclosed wherein chip density can be made extremely high, and the wafer can be processed while keeping a planar form as a whole.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了改进三维集成电路芯片或晶片组件的制造工艺，并且进一步详细地，可以在将芯片布置在晶片之前以晶片的阵列状态处理芯片为 叠加。 解决方案：公开了三维集成电路的制造，其中芯片密度可以非常高，并且可以在保持平面形状作为整体的同时处理晶片。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006344960A

公开(公告)日：2006-12-21

申请号：JP2006156597

申请日：2006-06-05

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  STEPHEN J HOLMES ,  HORAK DAVID V ,  MITCHELL PETER H

IPC: H01L21/027 ,  G03F7/20

Abstract: PROBLEM TO BE SOLVED: To provide an immersion lithography device and its method. SOLUTION: A lithographic optical column structure is disclosed for performing immersion lithography, at least on a projection optical system and a wafer of an optical system inside different fluids of equal pressure. In particular, a supercritical fluid is introduced to the periphery of the wafer with identical pressure, and another fluid, for example an inert gas, is introduced in at least the projection optical system of the optical system, thereby comprising the immersion lithography device which does not require special lenses. Furthermore, a chamber is provided which encloses the wafer to be exposed and at least a projection optical component of the optical system, and is filled with a supercritical immersion fluid. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：WO2008039166A2

公开(公告)日：2008-04-03

申请号：PCT/US2006028464

申请日：2006-07-21

Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/16 ,  G11C2213/77 ,  Y10S977/742 ,  Y10S977/939 ,  Y10S977/943

Abstract: Non-volatile and radiation-hard switching and memory devices (225) using vertical nano-tubes (155) and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract translation: 使用垂直纳米管（155）的非易失性和辐射硬的开关和存储器件（225）并且通过范德华力力可逆地保持状态和制造器件的方法。 用于感测装置状态的装置包括测量电容，以及隧穿和场发射电流。