公开(公告)号：US11367789B2

公开(公告)日：2022-06-21

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Sean T. Ma ,  Harold Kennel

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/778 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US11328988B2

公开(公告)日：2022-05-10

申请号：US16728887

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L27/12 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11276694B2

公开(公告)日：2022-03-15

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/207

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US11164785B2

公开(公告)日：2021-11-02

申请号：US16728903

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC: H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.

公开(公告)号：US20200335610A1

公开(公告)日：2020-10-22

申请号：US16957667

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20200294969A1

公开(公告)日：2020-09-17

申请号：US16355623

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Anh Phan ,  Caleb Shuan Chia Barrett ,  Jay Prakash Gupta ,  Nishant Gupta ,  Kaiwen Hsu ,  Byungki Jung ,  Srinivasa Aravind Killampalli ,  Justin Gary Railsback ,  Supanee Sukrittanon ,  Prashant Wadhwa

IPC: H01L25/065 ,  H01L27/085 ,  H01L29/78 ,  H01L21/84 ,  H01L27/06

Abstract: Disclosed herein are stacked transistors with dielectric between source/drain materials of different strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between source/drain materials of adjacent strata, and the dielectric material is conformal on underlying source/drain material.

公开(公告)号：US20200266218A1

公开(公告)日：2020-08-20

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US20200258881A1

公开(公告)日：2020-08-13

申请号：US16649712

申请日：2018-01-18

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/861 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66

Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

公开(公告)号：US10734511B2

公开(公告)日：2020-08-04

申请号：US16077742

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Rafael Rios

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/739 ,  H01L29/08

Abstract: An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.

公开(公告)号：US10651313B2

公开(公告)日：2020-05-12

申请号：US16325423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Matthew V. Metz ,  Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Sean T. Ma

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/24

Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.