公开(公告)号：US20160372560A1

公开(公告)日：2016-12-22

申请号：US15252125

申请日：2016-08-30

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/417 ,  H01L23/535 ,  G11C7/02 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract translation: 本公开的实施例提供了用于减小纳米线晶体管中的寄生电阻的接触技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的隔离层，包括在隔离层上形成的纳米线材料以提供晶体管沟道的沟道层，以及与沟道层耦合的接触点 被配置为在至少一个平面尺寸中围绕所述沟道层的纳米线材料并且为所述晶体管提供源极端子或漏极端子。

公开(公告)号：US09455150B2

公开(公告)日：2016-09-27

申请号：US14140042

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Patricio E. Romero ,  Gilbert Dewey

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: The present disclosure relates to a method of forming a semiconductor. The method includes heating a substrate in a reaction chamber, supplying to the reaction chamber a first constituent including a metal borohydride wherein the metal borohydride includes at least one of: an alkaline earth metal, a transition metal, or a combination thereof; supplying to the reaction chamber a main-group hydride constituent; and depositing a metal compound on the substrate, wherein the metal compound comprises a) at least one of an alkaline earth metal a transition metal or a combination thereof, b) boron and c) optionally the main group alloying element.

Abstract translation: 本公开涉及形成半导体的方法。 该方法包括加热反应室中的基材，向反应室供应包括金属硼氢化物的第一组分，其中金属硼氢化物包括以下中的至少一种：碱土金属，过渡金属或其组合; 向反应室供应主要的氢化物组分; 以及在基底上沉积金属化合物，其中金属化合物包括a）碱土金属过渡金属或其组合中的至少一种，b）硼和c）任选的主族合金元素。

公开(公告)号：US20160064520A1

公开(公告)日：2016-03-03

申请号：US14924643

申请日：2015-10-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/15 ,  H01L29/267

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US09263557B2

公开(公告)日：2016-02-16

申请号：US14069880

申请日：2013-11-01

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

IPC: H01L29/66 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/775 ,  H01L29/778 ,  H01L21/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/51

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US09219135B2

公开(公告)日：2015-12-22

申请号：US14057204

申请日：2013-10-18

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/775 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20150001644A1

公开(公告)日：2015-01-01

申请号：US14490581

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L29/51 ,  H01L21/768 ,  H01L21/324 ,  H01L21/285

CPC classification number: H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract translation: 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。

公开(公告)号：US08872160B2

公开(公告)日：2014-10-28

申请号：US13872966

申请日：2013-04-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

IPC: H01L29/06 ,  H01L29/80 ,  H01L29/78 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/66

CPC classification number: H01L29/7783 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7785 ,  H01L29/7848 ,  H01L29/802 ,  H01L29/803

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140231871A1

公开(公告)日：2014-08-21

申请号：US14263708

申请日：2014-04-28

Applicant: INTEL CORPORATION

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US20250133822A1

公开(公告)日：2025-04-24

申请号：US19001219

申请日：2024-12-24

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC: H10D84/85 ,  H01L21/02 ,  H01L21/28 ,  H10D30/01 ,  H10D30/67 ,  H10D30/69 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

公开(公告)号：US12224202B2

公开(公告)日：2025-02-11

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.