公开(公告)号：US11594673B2

公开(公告)日：2023-02-28

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Benjamin Buford ,  Tofizur Rahman ,  Rohan Patil ,  Nafees Kabir ,  Michael Christenson ,  Ian Young ,  Hui Jae Yoo ,  Christopher Wiegand

IPC: H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US11532719B2

公开(公告)日：2022-12-20

申请号：US16222946

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Willy Rachmady ,  Aaron Lilak ,  Brennen Mueller ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06

Abstract: Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer.

公开(公告)号：US20220344376A1

公开(公告)日：2022-10-27

申请号：US17864264

申请日：2022-07-13

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L27/22 ,  H01L27/24 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US11430814B2

公开(公告)日：2022-08-30

申请号：US16957047

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L27/22 ,  H01L27/24 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US11367749B2

公开(公告)日：2022-06-21

申请号：US16022564

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Atm G. Sarwar ,  Ian Young ,  Hui Jae Yoo ,  Christopher Wiegand ,  Benjamin Buford

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12 ,  H01F41/34

Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.

公开(公告)号：US20220189957A1

公开(公告)日：2022-06-16

申请号：US17117978

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le

IPC: H01L27/108 ,  G11C11/402 ,  H01L29/24

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US10763161B2

公开(公告)日：2020-09-01

申请号：US16702233

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L21/76 ,  H01L23/52 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US10546772B2

公开(公告)日：2020-01-28

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Richard E. Schenker ,  Hui Jae Yoo ,  Kevin L. Lin ,  Jasmeet S. Chawla ,  Stephanie A. Bojarski ,  Satyarth Suri ,  Colin T. Carver ,  Sudipto Naskar

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US09165824B2

公开(公告)日：2015-10-20

申请号：US14039893

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Christopher Jezewski ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract translation: 包括全覆层互连的金属化层和形成完全包层的互连的方法。 在电介质层中形成开口，其中介电层具有表面，并且开口包括壁和底部。 扩散阻挡层和粘合层沉积在介电层上。 互连材料沉积在介电层上并回流到形成互连的开口中。 在互连上沉积粘合覆盖层和扩散阻挡覆盖层。 互连被粘合层和粘合覆盖层包围，粘合层和粘合覆盖层被扩散阻挡层和扩散覆盖层包围。

公开(公告)号：US12224202B2

公开(公告)日：2025-02-11

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.