公开(公告)号：US11894270B2

公开(公告)日：2024-02-06

申请号：US17720152

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Sudipto Naskar ,  Manish Chandhok ,  Miriam Reshotko ,  Rami Hourani

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L21/76897 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5226

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US12176408B2

公开(公告)日：2024-12-24

申请号：US17131467

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Willy Rachmady ,  Hsin-Fen Li ,  Christopher Parker ,  Prashant Wadhwa ,  Tahir Ghani ,  Mohammad Hasan ,  Jianqiang Lin

IPC: H01L29/423 ,  B82Y10/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

公开(公告)号：US20240332299A1

公开(公告)日：2024-10-03

申请号：US18192601

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Van Le ,  Sudipto Naskar ,  Sukru Yemenicioglu

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: An integrated circuit device comprising a plurality of first field effect transistors (FETs) formed on a substrate, wherein a first FET comprises a first channel material comprising a portion of the substrate; and a plurality of second FETs formed on the substrate, wherein a second FET comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (TFT) channel material.

公开(公告)号：US20240332290A1

公开(公告)日：2024-10-03

申请号：US18129700

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Patrick Morrow ,  Nikhil Mehta ,  Leonard Guler ,  Sudipto Naskar ,  Alison Davis ,  Dan Lavric ,  Matthew Prince ,  Jeanne Luce ,  Charles Wallace ,  Cortnie Vogelsberg ,  Rajaram Pai ,  Caitlin Kilroy ,  Jojo Amonoo ,  Sean Pursel ,  Yulia Gotlib

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

公开(公告)号：US20240324167A1

公开(公告)日：2024-09-26

申请号：US18189808

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Abhishek Anil Sharma ,  Sukru Yemenicioglu ,  Weimin Han ,  Van Le

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A high performance (HP) thin film transistor (TFT) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (BEOL) processes. The HP TFT material is suitable for fabricating the memory stack at the lower BEOL temperatures while still delivering the switching speed requirements of a 3D memory stack in the CIM component. A through silicon via (TSV) architecture connects the logic and the memory in the die.

公开(公告)号：US20230163212A1

公开(公告)日：2023-05-25

申请号：US17531154

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Anand Murthy ,  Rushabh D. Shah ,  Sudipto Naskar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: An integrated circuit (IC) device, and a method of forming the same. The IC device includes a transistor device comprising a multilayer stack that has a plurality of channel layers including a semiconductor material; a gate structure wrapped at least partially around the channel layers, the gate structure including a metal; an epitaxial source structure at a first lateral end of the multilayer stack; an epitaxial drain structure at a second lateral end of the multilayer stack opposite the first lateral end; and inner spacers between the gate structure and respective ones of the source structure and the drain structure, wherein at least one of the source structure or the drain structure does not exhibit a pattern of crystallographic defects extending from the inner spacers.

公开(公告)号：US20220199458A1

公开(公告)日：2022-06-23

申请号：US17127860

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Michael Makowski ,  Sudipto Naskar ,  Ryan Pearce ,  Nita Chandrasekhar ,  Minyoung Lee ,  Christopher Parker

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

公开(公告)号：US11264449B2

公开(公告)日：2022-03-01

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11239112B2

公开(公告)日：2022-02-01

申请号：US16604681

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Sudipto Naskar ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.

公开(公告)号：US10546772B2

公开(公告)日：2020-01-28

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Richard E. Schenker ,  Hui Jae Yoo ,  Kevin L. Lin ,  Jasmeet S. Chawla ,  Stephanie A. Bojarski ,  Satyarth Suri ,  Colin T. Carver ,  Sudipto Naskar

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.