公开(公告)号：US11075207B2

公开(公告)日：2021-07-27

申请号：US16633061

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: G11C11/00 ,  H01L27/11 ,  G11C5/06 ,  G11C5/10 ,  G11C11/419

Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.

公开(公告)号：US11031072B2

公开(公告)日：2021-06-08

申请号：US16641574

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Prashant Majhi

IPC: G11C11/00 ,  G11C11/56 ,  H01L45/00 ,  H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/4096 ,  H01L27/108 ,  G11C14/00 ,  G11C11/40

Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

公开(公告)号：US10854746B2

公开(公告)日：2020-12-01

申请号：US16190135

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Khaled Hasnat ,  Krishna Parat

IPC: H01L29/792 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/11582 ,  H01L29/16 ,  H01L27/1157 ,  H01L21/28

Abstract: A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.

公开(公告)号：US10825861B2

公开(公告)日：2020-11-03

申请号：US16077603

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  James S. Clarke

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.

公开(公告)号：US20200235105A1

公开(公告)日：2020-07-23

申请号：US16633061

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: H01L27/11 ,  G11C11/419 ,  G11C5/06 ,  G11C5/10

Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.

公开(公告)号：US10680115B2

公开(公告)日：2020-06-09

申请号：US15772762

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Prashant Majhi

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.

公开(公告)号：US10651153B2

公开(公告)日：2020-05-12

申请号：US16011139

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Khaled Hasnat ,  Prashant Majhi ,  Owen Jungroth

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L25/065 ,  G11C16/08 ,  H01L23/00 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/06 ,  H01L27/11575 ,  H01L27/11582 ,  H01L25/00 ,  G11C5/02

Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

公开(公告)号：US20190333803A1

公开(公告)日：2019-10-31

申请号：US16475084

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Anup Pancholi ,  Prashant Majhi ,  Paul Fischer ,  Patrick Morrow

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/522

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

公开(公告)号：US20190326403A1

公开(公告)日：2019-10-24

申请号：US15956604

申请日：2018-04-18

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Prashant Majhi ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Brian S. Doyle ,  Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/24 ,  H01L29/861 ,  G01K7/34 ,  H01L29/16 ,  H01L29/20

Abstract: Electronic devices, integrated circuit device structures, and computing devices including thin film, diode-based temperature sensors are disclosed. An electronic device includes a diode including diode materials between a first contact and a second contact, a device layer of an integrated circuit device structure, and at least a portion of an interlayer dielectric between the diode and the device layer.

公开(公告)号：US10424620B2

公开(公告)日：2019-09-24

申请号：US15777535

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Ravi Pillarisetty ,  Uday Shah ,  Niloy Mukherjee

IPC: H01L27/24 ,  H01L45/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C13/00

Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.