公开(公告)号：US20150028408A1

公开(公告)日：2015-01-29

申请号：US13951099

申请日：2013-07-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

Abstract: An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion.

Abstract translation: 在半导体衬底中形成集成电路。 集成电路包括形成在半导体衬底的第一主表面中的沟槽。 沟槽包括第一沟槽部分和第二沟槽部分。 第一沟槽部分与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分的开口与第一主表面相邻。 集成电路还包括沟槽晶体管结构，其包括设置在第一沟槽部分中的栅电极和包括电容器电介质和第一电容器电极的沟槽电容器结构。 电容器电介质和第一电容器电极设置在第二沟槽部分中。 第一电容器电极包括与第二沟槽部分的侧壁共形的层。

公开(公告)号：US20140357048A1

公开(公告)日：2014-12-04

申请号：US13906425

申请日：2013-05-31

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/0696 ,  H01L21/28008 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66704 ,  H01L29/7813

Abstract: Methods for producing a semiconductor component that includes a transistor having a cell structure with a number of transistor cells monolithically integrated in a semiconductor body and electrically connected in parallel. In an example method, first trenches extending from the top side into the semiconductor body are produced, as are second trenches that each extend from the top side deeper into the semiconductor body than each of the first trenches. A first dielectric abutting on a first portion of the semiconductor body is produced at a surface of each of the first trenches. Also produced is a second dielectric at a surface of each of the second trenches. In each of the first trenches, a gate electrode is produced, after which a second portion of the semiconductor body is electrically insulated from the first portion of the semiconductor body by removing a bottom layer of the semiconductor body.

Abstract translation: 一种用于制造半导体元件的方法，该半导体元件包括晶体管，晶体管具有单个集成在半导体本体中并并联连接的多个晶体管单元的单元结构。 在示例性方法中，产生从顶侧延伸到半导体本体的第一沟槽，以及从第一沟槽中分别从第一沟槽的顶侧延伸到比第一沟槽中的每一个更深的半导体本体。 在每个第一沟槽的表面上产生邻接在半导体本体的第一部分上的第一电介质。 还产生在每个第二沟槽的表面处的第二电介质。 在每个第一沟槽中，制造栅电极，之后半导体本体的第二部分通过去除半导体本体的底层而与半导体本体的第一部分电绝缘。

公开(公告)号：US20140183629A1

公开(公告)日：2014-07-03

申请号：US13731380

申请日：2012-12-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

Abstract: A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a channel region, doped with dopants of a first conductivity type, a source region, a drain region, the source and the drain region being doped with dopants of a second conductivity type different from the first conductivity type, a drain extension region, and a gate electrode adjacent to the channel region. The channel region is disposed in a first portion of a ridge. The drain extension region is disposed in a second portion of the ridge, and includes a core portion doped with the first conductivity type. The drain extension region further includes a cover portion doped with the second conductivity type, the cover portion being adjacent to at least one or two sidewalls of the second portion of the ridge.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 晶体管包括掺杂有第一导电类型的掺杂剂的沟道区，源极区，漏极区，源极和漏极区掺杂有不同于第一导电类型的第二导电类型的掺杂剂;漏极延伸区 ，以及与沟道区相邻的栅电极。 通道区域设置在脊的第一部分中。 漏极延伸区域设置在脊的第二部分中，并且包括掺杂有第一导电类型的芯部分。 漏极延伸区域还包括掺杂有第二导电类型的覆盖部分，覆盖部分邻近脊部的第二部分的至少一个或两个侧壁。

公开(公告)号：US20140151798A1

公开(公告)日：2014-06-05

申请号：US13692059

申请日：2012-12-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区和与沟道区相邻的栅电极。 栅电极被配置为控制在沟道区中形成的沟道的导电率，沟道区和漂移区沿着源极区和漏极区之间的第一方向设置，第一方向平行于第一主表面 。 沟道区域具有沿着第一方向延伸的第一脊的形状，并且晶体管包括邻近漂移区布置的第一场板。

公开(公告)号：US20130230956A1

公开(公告)日：2013-09-05

申请号：US13850037

申请日：2013-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Markus Zundel

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.

Abstract translation: 一种方法包括形成从半导体主体的第一表面延伸到半导体本体中的沟槽，使得第一沟槽部分和与第一沟槽部分相邻的至少一个第二沟槽部分，其中第一沟槽部分比第二沟槽部分宽 。 第一电极在至少一个第二沟槽部分中形成，并且通过第一介电层与半导体本体的半导体区域介电绝缘。 在至少一个第二沟槽部分中，在第一电极上形成电极间电介质层。 第二电极形成在电极间电介质层的至少一个第二沟槽部分中，并且在第一沟槽部分中，使得至少在第一沟槽部分中的第二电极与半导体本体电介质绝缘 第二电介质层。

公开(公告)号：US12136670B2

公开(公告)日：2024-11-05

申请号：US17824198

申请日：2022-05-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L21/74 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/40

Abstract: A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.

公开(公告)号：US20220028980A1

公开(公告)日：2022-01-27

申请号：US17496050

申请日：2021-10-07

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder ,  Roland Rupp

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body, the trench structure having a gate electrode that is dielectrically insulated from the semiconductor body, a shielding region adjoining a bottom of the trench structure and forming a first pn junction with a drift structure of the semiconductor body, a body region forming a second pn junction with the drift structure, a source zone arranged between the first surface and the body region and forming a third pn junction with the source zone, wherein a contact portion of the body region extends to the first surface, wherein the source zone surrounds the contact portion of the body region at the first surface, and wherein the trench structure forms an enclosed loop at the first surface that surrounds the source zone and the contact portion of the body region at the first surface.

公开(公告)号：US20200161437A1

公开(公告)日：2020-05-21

申请号：US16193161

申请日：2018-11-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder

IPC: H01L29/40 ,  H01L29/16 ,  H01L29/872 ,  H01L29/78 ,  H01L29/423

Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.

公开(公告)号：US20190259870A1

公开(公告)日：2019-08-22

申请号：US16280775

申请日：2019-02-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/47 ,  H01L29/739 ,  H01L29/66 ,  H01L21/04 ,  H01L21/765

Abstract: A semiconductor device includes a trench structure extending from a first surface into a semiconductor body composed of silicon carbide. The trench structure includes an electrode and between the electrode and the first surface a gate electrode. A shielding region adjoining the electrode forms a first pn junction with a drift structure formed in the semiconductor body. A Schottky contact is formed between the drift structure and a first contact structure.

公开(公告)号：US20190157449A1

公开(公告)日：2019-05-23

申请号：US16235550

申请日：2018-12-28

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L29/78 ,  H01L23/48 ,  H01L27/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/74 ,  H01L29/66 ,  H01L29/45 ,  H01L29/861 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor body includes a first side and a second side opposite to the first side, a first dielectric disposed on the first side, a second dielectric disposed on the second side, one or more FET devices disposed at the first side, a first contact trench extending through the first dielectric at the first side, a first conductive material disposed in the first contact trench and electrically connected to the semiconductor body, a second contact trench extending through the second dielectric and into the semiconductor body at the second side, and a second conductive material disposed in the second contact trench and electrically connected to the semiconductor body at sidewalls of the second contact trench.