公开(公告)号：US20160181417A1

公开(公告)日：2016-06-23

申请号：US14976604

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Christian Kampen ,  Markus Zundel

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/407 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7813

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of field structures which define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric; a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; a plurality of body regions, a plurality of source regions, and a drift region. Each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region.

Abstract translation: 公开了一种晶体管器件。 晶体管器件包括在半导体本体中限定多个半导体台面区域的多个场结构，并且每个场结构包括场电极和场电极电介质; 每个半导体台面区域中的多个栅极结构，其中每个栅极结构包括栅电极和栅极电介质，并且布置在半导体台面区域的沟槽中; 多个体区域，多个源区域和漂移区域。 每个体区域与多个栅极结构中的至少一个栅极结构的栅极电介质相邻，并且位于多个源极区域中的一个和漂移区域之间。

公开(公告)号：US20140363940A1

公开(公告)日：2014-12-11

申请号：US14464849

申请日：2014-08-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

IPC: H01L21/383 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

Abstract: A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion.

Abstract translation: 晶体管通过在半导体衬底中形成包括第一脊部分和第二脊部分的脊而形成，所述脊部沿着第一方向延伸，形成源极区域，漏极区域，沟道区域，漏极延伸区域和 栅极与沟道区相邻，在脊中，掺杂具有第一导电类型的掺杂剂的沟道区，并用第二导电类型的掺杂剂掺杂源区和漏区。 形成漏极延伸区域包括在第二脊部中形成掺杂有第一导电类型的芯部分，并且形成漏极延伸区域还包括形成掺杂有第二导电类型的覆盖部分，盖部分形成为 邻近第二脊部分的至少一个或两个侧壁。

公开(公告)号：US10453915B2

公开(公告)日：2019-10-22

申请号：US15941637

申请日：2018-03-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Karl-Heinz Bach ,  Christian Kampen ,  Dietmar Kotz ,  Andrew Christopher Graeme Wood ,  Markus Zundel

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265

Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.

公开(公告)号：US09269592B2

公开(公告)日：2016-02-23

申请号：US14464849

申请日：2014-08-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

IPC: H01L21/383 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

Abstract: A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion.

Abstract translation: 晶体管通过在半导体衬底中形成包括第一脊部分和第二脊部分的脊而形成，所述脊部沿着第一方向延伸，形成源极区域，漏极区域，沟道区域，漏极延伸区域和 栅极与沟道区相邻，在脊中，掺杂具有第一导电类型的掺杂剂的沟道区，并用第二导电类型的掺杂剂掺杂源区和漏区。 形成漏极延伸区域包括在第二脊部中形成掺杂有第一导电类型的芯部分，并且形成漏极延伸区域还包括形成掺杂有第二导电类型的覆盖部分，盖部分形成为 邻近第二脊部分的至少一个或两个侧壁。

公开(公告)号：US08847311B2

公开(公告)日：2014-09-30

申请号：US13731380

申请日：2012-12-31

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

Abstract: A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a channel region, doped with dopants of a first conductivity type, a source region, a drain region, the source and the drain region being doped with dopants of a second conductivity type different from the first conductivity type, a drain extension region, and a gate electrode adjacent to the channel region. The channel region is disposed in a first portion of a ridge. The drain extension region is disposed in a second portion of the ridge, and includes a core portion doped with the first conductivity type. The drain extension region further includes a cover portion doped with the second conductivity type, the cover portion being adjacent to at least one or two sidewalls of the second portion of the ridge.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 晶体管包括掺杂有第一导电类型的掺杂剂的沟道区，源极区，漏极区，源极和漏极区掺杂有不同于第一导电类型的第二导电类型的掺杂剂;漏极延伸区 ，以及与沟道区相邻的栅电极。 通道区域设置在脊的第一部分中。 漏极延伸区域设置在脊的第二部分中，并且包括掺杂有第一导电类型的芯部分。 漏极延伸区域还包括掺杂有第二导电类型的覆盖部分，覆盖部分邻近脊部的第二部分的至少一个或两个侧壁。

公开(公告)号：US20200027969A1

公开(公告)日：2020-01-23

申请号：US16514292

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Christian Kampen ,  Andreas Meiser

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.

公开(公告)号：US09812563B2

公开(公告)日：2017-11-07

申请号：US15182244

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Markus Zundel ,  Karl-Heinz Bach ,  Franz Hirler ,  Christian Kampen ,  Werner Schustereder

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/7813 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66734

Abstract: A transistor cell includes, in a semiconductor body, a drift region of a first doping type, a source region of the first doping type, a body region of a second doping type, and a drain region of the first doping type. The body region is arranged between the source and drift regions. The drift region is arranged between the body and drain regions. A gate electrode is adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode is dielectrically insulated from the drift region by a field electrode dielectric. The drift region includes an avalanche region having a higher doping concentration than sections of the drift region adjacent the avalanche region and which is spaced apart from the field electrode dielectric in a direction perpendicular to the current flow direction. The field electrode is arranged in a needle-shaped trench.

公开(公告)号：US09698228B2

公开(公告)日：2017-07-04

申请号：US14976604

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Christian Kampen ,  Markus Zundel

IPC: H01L29/41 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/407 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7813

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of field structures which define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric; a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; a plurality of body regions, a plurality of source regions, and a drift region. Each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region.

公开(公告)号：US20140183629A1

公开(公告)日：2014-07-03

申请号：US13731380

申请日：2012-12-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

Abstract: A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a channel region, doped with dopants of a first conductivity type, a source region, a drain region, the source and the drain region being doped with dopants of a second conductivity type different from the first conductivity type, a drain extension region, and a gate electrode adjacent to the channel region. The channel region is disposed in a first portion of a ridge. The drain extension region is disposed in a second portion of the ridge, and includes a core portion doped with the first conductivity type. The drain extension region further includes a cover portion doped with the second conductivity type, the cover portion being adjacent to at least one or two sidewalls of the second portion of the ridge.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 晶体管包括掺杂有第一导电类型的掺杂剂的沟道区，源极区，漏极区，源极和漏极区掺杂有不同于第一导电类型的第二导电类型的掺杂剂;漏极延伸区 ，以及与沟道区相邻的栅电极。 通道区域设置在脊的第一部分中。 漏极延伸区域设置在脊的第二部分中，并且包括掺杂有第一导电类型的芯部分。 漏极延伸区域还包括掺杂有第二导电类型的覆盖部分，覆盖部分邻近脊部的第二部分的至少一个或两个侧壁。

公开(公告)号：US11145745B2

公开(公告)日：2021-10-12

申请号：US16514292

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Christian Kampen ,  Andreas Meiser

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/06

Abstract: A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.