公开(公告)号：WO9905782A3

公开(公告)日：1999-04-15

申请号：PCT/US9814998

申请日：1998-07-20

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  MARTIN CHRIS G

IPC: G11C7/06 ,  G11C29/00

CPC classification number: G11C7/065 ,  G11C7/062

Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complementary data signals at their differential inputs. In the altered mode, the mode control circuit couples a reference voltage to the second inputs of the sense amplifiers in the first stage so that the sense amplifiers compare a respective data signal to the reference voltage. The mode control circuit also alters the operation of the second stage. In the normal mode, the mode control circuit couples an output signal from the other sense amplifier in the first stage to a respective second input of each sense amplifier in the second stage so that the sense amplifiers receive at their differential inputs both of the complementary output signals from each sense amplifier in the first stage. In the altered mode, the mode control circuit couples a data signal to the respective second input of each sense amplifier in the second stage so that the sense amplifiers compare an output signal from a respective sense amplifier in the first stage to a respective data signal.

Abstract translation: 一种用于在正常模式或改变模式下放大数据信号的读出放大器。 在正常模式下，数据信号必须彼此互补，而在改变模式中，数据信号可以彼此互补，但不一定互补。 读出放大器包括两个读出放大器级，其中第一个驱动第二个，每个读出放大器级包括两个相同的读出放大器电路。 第一级中的每个读出放大器的第一输入接收相应的数据信号，并且第二级中的每个读出放大器的第一输入在第一级接收来自相应读出放大器的输出信号。 在正常模式中，模式控制电路将其它数据信号中的每一个耦合到第一级中每个读出放大器的相应第二输入端，使得读出放大器在其差分输入端接收两个互补数据信号。 在改变的模式中，模式控制电路在第一级将参考电压耦合到读出放大器的第二输入端，使得读出放大器将相应的数据信号与参考电压进行比较。 模式控制电路还改变第二级的操作。 在正常模式中，模式控制电路在第二级将来自第一级的另一个读出放大器的输出信号耦合到第二级的每个读出放大器的相应的第二输入端，使得读出放大器在其差分输入处接收两个互补输出 来自第一级的每个读出放大器的信号。 在改变模式中，模式控制电路将数据信号耦合到第二级中每个读出放大器的相应第二输入端，使得读出放大器将来自第一级的相应读出放大器的输出信号与相应的数据信号进行比较。

公开(公告)号：EP2864889A4

公开(公告)日：2016-07-13

申请号：EP13807412

申请日：2013-06-21

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  LARSEN TROY D ,  CULLEY MARTIN L ,  MEADER JEFFREY L ,  BARD STEVE G ,  EYRES DEAN C

IPC: G06F12/00

CPC classification number: G06F3/0608 ,  G06F3/0661 ,  G06F3/0673 ,  H03M7/30 ,  H03M7/60 ,  H03M7/6082

Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

公开(公告)号：EP2684132A4

公开(公告)日：2014-12-10

申请号：EP12754482

申请日：2012-03-01

Applicant: MICRON TECHNOLOGY INC

Inventor： CULLEY MARTIN L ,  MANNING TROY A ,  LARSEN TROY D

IPC: G06F12/02 ,  G06F12/04 ,  G06F12/14 ,  G06F13/14

CPC classification number: G06F3/0665 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/04 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1408 ,  G06F12/1475 ,  G06F2212/7201 ,  G06F2212/7202 ,  Y02B60/1225 ,  Y02D10/13

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract translation: 本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用与在写入与范围相关联的数据时跳过的多个物理位置的对应的RAM将数据转换到存储器中的物理位置 的特定范围以外的。

公开(公告)号：EP3167448A4

公开(公告)日：2018-03-21

申请号：EP15802782

申请日：2015-06-02

Applicant: MICRON TECHNOLOGY INC

Inventor： WHEELER KYLE B ,  MANNING TROY A ,  MURPHY RICHARD C

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

公开(公告)号：EP3152758A4

公开(公告)日：2018-01-24

申请号：EP15802631

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  MURPHY RICHARD C

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.

公开(公告)号：EP3031050A4

公开(公告)日：2017-05-24

申请号：EP14834674

申请日：2014-08-06

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/06 ,  G11C7/10 ,  H03K19/00 ,  H03K19/177

CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Abstract translation: 本公开内容包括涉及使用感测电路进行逻辑运算的方法和装置。 一个示例设备包括存储器单元的阵列和感测电路，其包括耦合到所述阵列的感测线的主锁存器。 感测电路可以被配置成通过感测耦合到所述感测线的存储器单元以执行逻辑操作的第一操作阶段，通过感测耦合到所述不同存储器单元的一个respectivement数执行多个逻辑运算的中间操作阶段的 感测线，并且累积在第一操作阶段和中间操作阶段的在耦合到主闩锁，而不执行的感测线地址访问的辅助锁存器的数量的结果。

公开(公告)号：EP1886155A4

公开(公告)日：2008-12-10

申请号：EP06752317

申请日：2006-05-04

Applicant: MICRON TECHNOLOGY INC

Inventor： JOHNSON JAMES B ,  MANNING TROY A

IPC: G11C7/10 ,  G01R31/26 ,  G11C29/02

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/105 ,  G11C2207/2254

Abstract: A synchronous dynamic random access memory ('SDRAM') device (100) includes a pipelined write data path coupling data from a data bus to a DRAM array (122), and a pipelined read data path coupling read data from the array ((122) to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without firs being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.

公开(公告)号：WO2015187609A3

公开(公告)日：2017-04-06

申请号：PCT/US2015033655

申请日：2015-06-02

Applicant: MICRON TECHNOLOGY INC

Inventor： WHEELER KYLE B ,  MANNING TROY A ,  MURPHY RICHARD C

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract translation: 本公开的一个示例包括使用存储在耦合到存储器阵列的感测线的多个存储器单元的第一部分中的第一值的逻辑表示和存储的第二值的逻辑表示来在存储器中执行比较操作 在耦合到存储器阵列的感测线的存储器单元的数量的第二部分中。 比较操作将第一值与第二值进行比较，并且该方法可以包括将比较操作的结果的逻辑表示存储在耦合到存储器阵列的感测线的存储器单元的数量的第三部分中。

公开(公告)号：WO2012166723A2

公开(公告)日：2012-12-06

申请号：PCT/US2012039846

申请日：2012-05-29

Applicant: MICRON TECHNOLOGY INC ,  RATNAM SAMPATH K ,  LARSEN TROY D ,  RIVERS DOYLE W ,  MANNING TROY A ,  CULLEY MARTIN L

Inventor： RATNAM SAMPATH K ,  LARSEN TROY D ,  RIVERS DOYLE W ,  MANNING TROY A ,  CULLEY MARTIN L

IPC: G06F12/16 ,  G11C7/24

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/0483

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.

Abstract translation: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。 第二位置可以不同于第二位置和第一存储块的第一位置。

公开(公告)号：WO2012121968A2

公开(公告)日：2012-09-13

申请号：PCT/US2012027265

申请日：2012-03-01

Applicant: MICRON TECHNOLOGY INC ,  CULLEY MARTIN L ,  MANNING TROY A ,  LARSEN TROY D

Inventor： CULLEY MARTIN L ,  MANNING TROY A ,  LARSEN TROY D

IPC: G06F12/02 ,  G06F13/14

CPC classification number: G06F3/0665 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/04 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1408 ,  G06F12/1475 ,  G06F2212/7201 ,  G06F2212/7202 ,  Y02B60/1225 ,  Y02D10/13

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract translation: 本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。