公开(公告)号：US11698864B2

公开(公告)日：2023-07-11

申请号：US17824676

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Abdelhakim Alhussien ,  Jiangang Wu ,  Karl D. Schuh ,  Qisong Lin ,  Jung Sheng Hoei

IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/02 ,  G11C11/408 ,  G06F9/30 ,  G06F9/4401

CPC classification number: G06F12/0882 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/4418 ,  G06F12/0246 ,  G11C11/4085

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

公开(公告)号：US20220404979A1

公开(公告)日：2022-12-22

申请号：US16954156

申请日：2020-03-10

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jing Sang Liu ,  Yun Li ,  James P. Crowley

IPC: G06F3/06

Abstract: Methods, systems, and devices for managing queues of a memory sub-system are described. A first command can be assigned to a first queue of a memory die of a memory sub-system. The first queue can be is associated with a first priority level and the memory die can include a second queue associated with a second priority level different from the first priority level. The second queue can include a second command, where the first command and the second command are each associated with a respective operation to be performed on the memory sub-system. In some examples, the first command can be issued before the second command based on the first and second priority levels.

公开(公告)号：US11527294B2

公开(公告)日：2022-12-13

申请号：US17001769

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Jiangang Wu

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/14 ,  G11C29/10 ,  G06F12/02 ,  G11C16/26

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

公开(公告)号：US20220392547A1

公开(公告)日：2022-12-08

申请号：US17820792

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl Schuh ,  Mustafa N. Kaynak ,  Xiangang Luo ,  Shane Nowell ,  Devin Batutis ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Jiangang Wu ,  Peter Feeley

IPC: G11C16/30 ,  G11C7/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/32 ,  G11C16/10

Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

公开(公告)号：US20220375530A1

公开(公告)日：2022-11-24

申请号：US17880980

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/26

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

公开(公告)号：US11455109B2

公开(公告)日：2022-09-27

申请号：US17160144

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

公开(公告)号：US20220291849A1

公开(公告)日：2022-09-15

申请号：US17751026

申请日：2022-05-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mastafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F3/06

Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

公开(公告)号：US20220229564A1

公开(公告)日：2022-07-21

申请号：US17715433

申请日：2022-04-07

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Gary F. Besinga ,  Cory M. Steinmetz ,  Pushpa Seetamraju ,  Jiangang Wu ,  Sampath K. Ratnam ,  Peter Feeley

IPC: G06F3/06

Abstract: A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.

公开(公告)号：US11301143B2

公开(公告)日：2022-04-12

申请号：US16432786

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Gary F. Besinga ,  Cory M. Steinmetz ,  Pushpa Seetamraju ,  Jiangang Wu ,  Sampath K. Ratnam ,  Peter Feeley

IPC: G06F3/06

Abstract: A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.

公开(公告)号：US20220084605A1

公开(公告)日：2022-03-17

申请号：US16948359

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/26

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.