公开(公告)号：US11315918B2

公开(公告)日：2022-04-26

申请号：US16865429

申请日：2020-05-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L27/02 ,  H01L27/112 ,  H01L23/528 ,  H01L23/525 ,  H01L23/522

Abstract: A semiconductor layout structure includes a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, in which the active regions are separated from each other by an isolation structure. The transistors are respectively disposed in the active regions. The gate structures extend across the active regions along a second direction that is perpendicular to the first direction, in which each of the active regions includes a pair of source/drain portions at opposite sides of each of the gate structures. The conductive structures are embedded in a first portion of the isolation structure disposed between the adjacent active regions in the first direction, wherein the conductive structures extend along the second direction and are separated from the source/drain portions by the isolation structure.

公开(公告)号：US11183502B1

公开(公告)日：2021-11-23

申请号：US16997938

申请日：2020-08-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: G11C17/16 ,  H01L27/112 ,  G11C17/18 ,  H01L23/525

Abstract: A memory cell includes a semiconductor substrate, a transistor, and a first anti-fuse structure. The transistor is above the semiconductor substrate. The first anti-fuse structure is above the semiconductor substrate and adjacent the transistor, and includes a first terminal and a second terminal. The first terminal of the first anti-fuse structure is in the semiconductor substrate and laterally surrounds the transistor. The second terminal of the first anti-fuse structure is above and spaced apart from the first terminal of the first anti-fuse structure.

公开(公告)号：US11107730B1

公开(公告)日：2021-08-31

申请号：US16865428

申请日：2020-05-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/112 ,  H01L21/84

Abstract: A method of manufacturing a semiconductor structure including following operations is provided. A substrate extending along a first direction is provided. A trench crossing the substrate is then formed to define a first active region and a second active region. A lower isolation structure is formed in the trench, in which the lower isolation structure exposes a portion of a sidewall of the substrate. The exposed sidewall of the substrate is oxidized to form an upper isolation structure on the lower isolation structure, in which the upper isolation structure extends into the substrate. A conductive structure embedded in the upper isolation structure is formed. A first transistor and a second transistor are respectively formed in the first active region and the second active region.

公开(公告)号：US10833029B2

公开(公告)日：2020-11-10

申请号：US16217800

申请日：2018-12-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu ,  Ting-Cih Kang

IPC: H01L23/66 ,  H01L49/02

Abstract: The present disclosure relates to an electronic device and a method of manufacturing a filtering component of the electronic device. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.

公开(公告)号：US10825796B2

公开(公告)日：2020-11-03

申请号：US16166803

申请日：2018-10-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a device chip and a protecting material. The device chip has an active area and an inactive area arranged around the active area. The protecting material includes a first portion and a second portion, the first portion is disposed within the inactive area and encircles the active area, and the second portion is disposed over a lower surface of the device chip.

公开(公告)号：US10818541B2

公开(公告)日：2020-10-27

申请号：US16363374

申请日：2019-03-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/764 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a semiconductor substrate, an air gap region, a capping layer, and an isolating layer. The air gap region is disposed in the semiconductor substrate. The capping layer is disposed on the air gap region. The isolating layer is disposed on the semiconductor substrate and partially encircles the capping layer.

公开(公告)号：US12278179B2

公开(公告)日：2025-04-15

申请号：US18209101

申请日：2023-06-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: H01L23/525 ,  H01L23/528 ,  H10D30/01 ,  H10D30/60 ,  H10D62/13 ,  H10D64/01 ,  H10D64/23 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/40 ,  H10D84/83

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

公开(公告)号：US12267994B2

公开(公告)日：2025-04-01

申请号：US17707445

申请日：2022-03-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H10B12/00 ,  G11C11/406

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate. The substrate comprises a first well region having a first conductive type. The method also includes forming a first gate structure on the substrate. The method further includes forming a first doped region in the substrate. The first doped region has a second conductive type different from the first conductive type. The first gate structure and the first doped region are included in a first transistor. In addition, the method includes forming a capacitor structure electrically coupled to the first doped region of the substrate. The method also includes forming a second doped region in the substrate. The second doped region has the second conductive type, the second doped region and the first well region collectively serve a diode, and the second doped region is electrically coupled to the first electrode of the capacitor structure and the first doped region.

公开(公告)号：US12262551B2

公开(公告)日：2025-03-25

申请号：US18611718

申请日：2024-03-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L21/02 ,  H10D62/10 ,  H10D64/68

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

公开(公告)号：US12185529B2

公开(公告)日：2024-12-31

申请号：US17678407

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: H10B20/20

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.