公开(公告)号：US11756988B2

公开(公告)日：2023-09-12

申请号：US16997954

申请日：2020-08-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01L49/02 ,  H01L23/522 ,  H01G4/30

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L23/5223

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US10886236B1

公开(公告)日：2021-01-05

申请号：US16544887

申请日：2019-08-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L23/528 ,  H01L23/552 ,  H01L23/522

Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.

公开(公告)号：US12183715B2

公开(公告)日：2024-12-31

申请号：US17546283

申请日：2021-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure employing a via structure. The method includes forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, The via structure contacts the second conductive pad, and the first conductive pad and the second conductive pad are formed of different metal materials.

公开(公告)号：US12027575B2

公开(公告)日：2024-07-02

申请号：US18333507

申请日：2023-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01G4/30 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L23/5223

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US11307249B1

公开(公告)日：2022-04-19

申请号：US17136777

申请日：2020-12-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: G01R31/28 ,  G01R27/08 ,  G01R31/30

Abstract: The present application discloses a method for characterizing a resistance state of a programmable element of an integrated circuit. The method includes the steps of setting a first programming voltage of a first polarity to program the programmable element of the integrated circuit, setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current, setting the first read voltage of the first polarity to the integrated circuit at a second temperature to obtain a second read current, the second temperature is at least 50° C. higher than the first temperature, and a second resistance is derived from the second read current, and comparing the first resistance and the second resistance to characterize the resistance state of the programmable element.

公开(公告)号：US12262551B2

公开(公告)日：2025-03-25

申请号：US18611718

申请日：2024-03-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L21/02 ,  H10D62/10 ,  H10D64/68

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

公开(公告)号：US12033956B2

公开(公告)日：2024-07-09

申请号：US17808300

申请日：2022-06-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L23/5226 ,  H01L23/5283

Abstract: An interconnect structure includes first, second, and third insulating layers, first, second, and third conductive lines, and first, second, third, and fourth conductive vias. The first conductive line is embedded in the first insulating layer. The second conductive line is embedded in the second insulating layer and comprises a first portion, a second portion, and a third portion. The third conductive line is embedded in the third insulating layer. The first and second conductive via are embedded in the first insulating layer. The third and fourth conductive via are embedded in the second insulating layer. A first cross-sectional area surrounded by the first conductive line, the first conductive via, the second conductive via, the first portion, and the second portion is substantially equal to a second cross-sectional area surrounded by the first portion, the third portion, the third conductive via, the fourth conductive via, and the third conductive line.

公开(公告)号：US11967612B2

公开(公告)日：2024-04-23

申请号：US17643417

申请日：2021-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/02008 ,  H01L29/517

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

公开(公告)号：US11456353B2

公开(公告)日：2022-09-27

申请号：US16930328

申请日：2020-07-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L29/51 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

公开(公告)号：US11574880B2

公开(公告)日：2023-02-07

申请号：US17061397

申请日：2020-10-01

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu ,  Ting-Cih Kang

IPC: H01L21/8242 ,  H01L23/66 ,  H01L49/02

Abstract: The present disclosure relates to an electronic device with an integral filtering component. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.