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公开(公告)号：BR0101472B1
公开(公告)日：2014-08-12
申请号：BR0101472
申请日：2001-04-12
Applicant: SONY CORP
Inventor： OKADA TAKAHIRO , MIYATO YOSHIKAZU , IKEDA YASUNARI , IKEDA TAMOTSU
Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.
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公开(公告)号：DE69835254T2
公开(公告)日：2007-06-14
申请号：DE69835254
申请日：1998-04-30
Applicant: SONY CORP
Inventor： HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA YASUNARI
Abstract: A technique for receiving an OFDM signal is arranged to accurately reproduce a clock signal. I channel data and Q channel data are differential-demodulated by a differential demodulation circuit (503) and are supplied to a ROM (512). The ROM (512) reads out an intersymbol phase change amount corresponding to the differential-demodulated data and supplies it to a gate circuit (514) which extracts only a component corresponding to each one of pilot signals in the input data, and supplies the extracted component to a sign inversion circuit (521) and to a selector (522). The selector (522) selects the output from the gate circuit (514) if the pilot signal is a positive frequency value, or the output from the sign inversion circuit (521) if the pilot signal is a negative frequency value, and supplies the obtained value to a cumulative addition circuit (515). The cumulative addition circuit (515) performs cumulative addition of values output from the selector (522) over a symbol period, and outputs the addition result to an average circuit (516). The average circuit (516) averages the output from the cumulative addition circuit (515) and controls the frequency of oscillation of a clock signal according to a value obtained by the average circuit (516).
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公开(公告)号：DE69531234T2
公开(公告)日：2004-04-22
申请号：DE69531234
申请日：1995-08-31
Applicant: SONY CORP
Inventor： IKEDA TAMOTSU , IKEDA YASUNARI , OKADA TAKAHIRO
Abstract: The present invention is used for example digital television broadcasting and provides a good television picture and sound where the signal level is large on the reception side and provides a television picture and sound of a certain degree of quality even in a case where the signal level is small. The signal transmitting apparatus (10) divides the series of input information in accordance with the significance of the content of the data to obtain a plurality of input signals, encodes the input signals with respectively different encoding rates, multiplexes the same at the time slots for transmission, modulates the same by multi-value modulation methods different for every time slot corresponding to the coded signals, and transmits the resultant data via the communication transmission line (20) such as a satellite communication channel to the signal receiving apparatus (30). The signal receiving apparatus (30) demodulates the respective coded signals from the modulated signals received from the communication transmission line (20) by demodulation methods different for every time slot corresponding to the coded signals contained in the received signals, demultiplexes the same, decodes the result, and reproduces the respective input signals.
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公开(公告)号：DE69531234D1
公开(公告)日：2003-08-14
申请号：DE69531234
申请日：1995-08-31
Applicant: SONY CORP
Inventor： IKEDA TAMOTSU , IKEDA YASUNARI , OKADA TAKAHIRO
Abstract: The present invention is used for example digital television broadcasting and provides a good television picture and sound where the signal level is large on the reception side and provides a television picture and sound of a certain degree of quality even in a case where the signal level is small. The signal transmitting apparatus (10) divides the series of input information in accordance with the significance of the content of the data to obtain a plurality of input signals, encodes the input signals with respectively different encoding rates, multiplexes the same at the time slots for transmission, modulates the same by multi-value modulation methods different for every time slot corresponding to the coded signals, and transmits the resultant data via the communication transmission line (20) such as a satellite communication channel to the signal receiving apparatus (30). The signal receiving apparatus (30) demodulates the respective coded signals from the modulated signals received from the communication transmission line (20) by demodulation methods different for every time slot corresponding to the coded signals contained in the received signals, demultiplexes the same, decodes the result, and reproduces the respective input signals.
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公开(公告)号：AU3517801A
公开(公告)日：2001-10-18
申请号：AU3517801
申请日：2001-04-12
Applicant: SONY CORP
Inventor： OKADA TAKAHIRO , IKEDA TAMOTSU , IKEDA YASUNARI , MIYATO YOSHIKAZU
Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.
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Patent Agency Ranking
公开(公告)号：AU2692300A
公开(公告)日：2000-09-14
申请号：AU2692300
申请日：2000-02-25
Applicant: SONY CORP , JAPAN BROADCASTING CORP , KENICHI TSUCHIDA , MAKOTO SASAKI
Inventor： TSUCHIDA KENICHI , SASAKI MAKOTO , IKEDA YASUNARI , HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA TAMOTSU , KURODA TORU , IAI NAOHIKO
Abstract: A frequency interleaving circuit frequency-interleaves main signals generated according to sound data by parameters set according to frequencies of transmission channels. A sub-signal generating circuit generates sub-signals for transmission control including pilot signals. Mapping circuits modulate the sub-signals by using pseudo-random sequences generated based on initial values of random codes set according to frequencies of transmission channels. The frequency-interleaved main signals and the sub-signals modulated by the mapping circuits are OFDM-modulated. Then, they are converted to the frequencies of the transmission channels. An increase of a dynamic range of transmission signals can be suppressed by controlling the initial values of random codes set.
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公开(公告)号：AU6378498A
公开(公告)日：1998-11-05
申请号：AU6378498
申请日：1998-05-01
Applicant: SONY CORP
Inventor： HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA YASUNARI
Abstract: A technique for receiving an OFDM signal is arranged to accurately reproduce a clock signal. I channel data and Q channel data are differential-demodulated by a differential demodulation circuit (503) and are supplied to a ROM (512). The ROM (512) reads out an intersymbol phase change amount corresponding to the differential-demodulated data and supplies it to a gate circuit (514) which extracts only a component corresponding to each one of pilot signals in the input data, and supplies the extracted component to a sign inversion circuit (521) and to a selector (522). The selector (522) selects the output from the gate circuit (514) if the pilot signal is a positive frequency value, or the output from the sign inversion circuit (521) if the pilot signal is a negative frequency value, and supplies the obtained value to a cumulative addition circuit (515). The cumulative addition circuit (515) performs cumulative addition of values output from the selector (522) over a symbol period, and outputs the addition result to an average circuit (516). The average circuit (516) averages the output from the cumulative addition circuit (515) and controls the frequency of oscillation of a clock signal according to a value obtained by the average circuit (516).
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公开(公告)号：AU572602B2
公开(公告)日：1988-05-12
申请号：AU3671084
申请日：1984-11-19
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , NAKANO HIROSHI , YUCHI HIROFUMI
Abstract: PCT No. PCT/JP84/00553 Sec. 371 Date Jul. 18, 1985 Sec. 102(e) Date Jul. 18, 1985 PCT Filed Nov. 19, 1984 PCT Pub. No. WO85/02511 PCT Pub. Date Jun. 6, 1985.A television receiver in which a video signal of an interlaced system is received and converted in field frequency by using field memories (6a) and (6b) and then fed to a picture receiving tube (9). In this case, the picture receiving tube (9) is subjected to a vertical deflection scanning by a vertical synchronizing signal of a constant period and the video signal in each field of the video signal to be supplied to the picture receiving tube (9) is delayed by a predetermined time by controlling, for example, the read-out timings of the field memories (6a) and (6b) to thereby keep an interlace-ratio constant. Consequently, since the respective vertical cycles are equal to one another, even if the parabolic current wave of the vertical cycle for deflection correcting, for example, is superposed on the horizontal deflecting current, the horizontal deflection current waveform is equal in each vertical period so that the jitter can be prevented from being produced at the right and left ends of the picture screen.
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69.发明专利
公开(公告)号：AU549977B2
公开(公告)日：1986-02-20
申请号：AU9065482
申请日：1982-11-17
Applicant: SONY CORP
Inventor： OKADA TAKASHI , IKEDA YASUNARI , TANAKA YUTAKA
Abstract: A double-scanning non-interlace television receiver with a vertical aperture correction circuit for receiving an interlace television signal having alternating odd and even fields of scanned lines which are interlaced, as displayed, comprises a receiver circuit which receives the interlace television signal and which generates interlace scanning line signals for each of the fields, a visual display apparatus, a non-interlace converting circuit which converts the interlace scanning line signals for each of the fields to non-interlace scanning line signals which are displayed on the visual display apparatus, with each of the scanned lines being scanned twice, and a high frequency emphasizing circuit which emphasizes the high frequency components of the interlace scanning line signals.
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70.发明专利
公开(公告)号：CA1192300A
公开(公告)日：1985-08-20
申请号：CA415775
申请日：1982-11-17
Applicant: SONY CORP
Inventor： OKADA TAKASHI , IKEDA YASUNARI , TANAKA YUTAKA
Abstract: DOUBLE-SCANNING NON-INTERLACE TELEVISION RECEIVER WITH VERTICAL APERTURE CORRECTION CIRCUIT A double scanning non-interlace television receiver with a vertical aperture correction circuit for receiving an interlace television signal having alternating odd and even fields of scanned lines which are interlaced, as displayed, comprises a receiver circuit which receives the interlace television signal and which generates interlace scanning line signals for each of the fields, a visual display apparatus, a non-interlace converting circuit which converts the interlace scanning line signals for each of the fields to non-interlace scanning line signals which are displayed on the visual display apparatus, with each of the scanned lines being scanned twice, and a high frequency emphasizing circuit which emphasizes the high frequency components of the interlace scanning line signals.
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