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    61.
    发明专利
    未知

    公开(公告)号：FR2813698A1

    公开(公告)日：2002-03-08

    申请号：FR0011242

    申请日：2000-09-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C15/04 ,  G11C11/40 ,  G06F12/08

    Abstract: The content-addressed memory cell comprises the first storage subcell with transistors (T1,T2) in series and inverters (INV1,INV2) in antiparallel connection, a comparison subcell with transistors (PA,PB) in series controlling a transistor (PC) which is connected in series with a blocking transistor (PD), and the second storage subcell with transistors (T3,T4) in series and inverters (INV3,INV4) in antiparallel connection controlling the blocking transistor (PD). The transistors (T1,T2,T3,T4) are with n-type conductivity channel, and the transistors (PA,PB,PC,PD) are with p-type conductivity channel. The memory cell is implemented in the form of an integrated circuit wherein the transistors with p-type conductivity channel are implemented in the same n-type well which occupies substantially half of the cell surface. The first storage subcell is connected between the first set of bit lines (BL1,/BL1), and the gates of transistors (T1,T2) are connected to the first word line (WL1). The second storage subcell is connected between the second set of bit lines (BL2,/BL2), and the gates of transistors (T3,T4) are connected to the second word line (WL2). The blocking transistor (PD) is connected to the match line (MATCH). In the integrated circuit implementation, the transistors (T1,T2,T3,T4) are implemented in a substantially aligned fashion, the same as the n-type transistors of inverters (INV1,INV2,INV3,INV4), and the transistors (PA,PB,PC,PD) are also implemented in a substantially aligned fashion as well as the p-type transistors of inverters (INV1,INV2,INV3,INV4).

    Memory circuit comprising redundant cells placed outside memory blocks and connected to blocks as required by control, for use in information technology
    62.
    发明专利
    Memory circuit comprising redundant cells placed outside memory blocks and connected to blocks as required by control, for use in information technology 未知

    公开(公告)号：FR2811464A1

    公开(公告)日：2002-01-11

    申请号：FR0008746

    申请日：2000-07-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C29/00 ,  G11C7/24

    Abstract: The memory circuit comprises a number of blocks (4), e.g. 8 of which 3 are represented, of memory cells organized in rows and columns, and at least one redundant row (16') formed by redundant memory cells and placed outside the blocks of memory circuit. The memory circuit also comprises a control block (18') for invalidating the writing/reading of a defective memory cell of any block of the memory circuit and for allowing after replacement the writing/reading of a memory cell of the redundant row. Each block (4) is adjoined by a rows decoder (8), and the control block (18') is connected to the rows decoder of each block for invalidating the writing/ reading of defective memory cell. The memory cells of rows of blocks and the redundant row form words, and a word of a row of any block containing a defective cell is replaced by a word of the redundant row. A row of any block containing defective memory cell is replaced by one of the redundant rows. Each redundant memory cell is of a static memory type.

    63.
    发明专利
    未知

    公开(公告)号：FR2784219B1

    公开(公告)日：2001-11-02

    申请号：FR9811715

    申请日：1998-09-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02 ,  G11C11/401

    Abstract: The memory realized in an integrated circuit chip (2') comprises a matrix network of cells divided in sections (S), rows of amplifiers for column decoding (CDEC) with outputs interconnected to decoded bit lines, each comprising two perpendicular sections, one in the row direction for connecting directly each decoded bit line to the input/output (I/O) stage at the extremity of rows. The circuits for row decoding (RDEC), predecoding (PREDEC), input/output (I/O), and control (CONTROL) are located in the same section as the bus for address (ADD), data (DATA) and control (CTR) signals. The change of direction within two sections of the bit line is carried out without active element, by direct interconnection. The memory cell contains a transistor connected to a capacitor, and the amplifier for column decoding is directly connected to the local bit line interconnecting the drains of transistors in the same section. The circuits (PREDEC, RDEC, I/O) can be located on both sides of the integrated circuit chip. The number of rows of memory cells per section is selected to have the signal/noise ratio higher than 1/10 at inputs of amplifiers for column decoding.

    Logic cell for unique programming with reduced power consumption
    64.
    发明专利
    Logic cell for unique programming with reduced power consumption 未知

    公开(公告)号：FR2797086A1

    公开(公告)日：2001-02-02

    申请号：FR9910090

    申请日：1999-07-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C17/18 ,  H03K19/00 ,  H03K19/0185 ,  G11C17/16

    Abstract: The unique programming cell comprises an inverter (16) delivering a logic state as a function of the cell state, a fuse (10) connected between the first supply potential (Vss) and the input (A) of inverter, and a constant current source (14) connected between the fuse and the second supply potential (Vdd). The inverter is power-fed on the account of second supply potential via a transistor (MP3) connected as a diode, and the constant current source is constituted by a second transistor controlled by the inverter output (S). The second transistor has the voltage threshold higher than the first transistor. The first and second transistors are of MOS type with p-type conductivity channel, and the second supply potential (Vdd) is the higher potential. The channel length of second transistor (14) is greater than that of the first transistor (MP3). The unique programming cell also comprises an initialization transistor (MN1) connecting the node (A) to the first supply potential (Vss). The inverter comprises two MOS transistors (MN2, MP2) connected in series, with the common gate connection as input (A) and the common drain connection as output (S).

    65.
    发明专利
    未知

    公开(公告)号：FR2785080B1

    公开(公告)日：2001-01-19

    申请号：FR9813546

    申请日：1998-10-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： JAOUEN HERVE ,  FERRANT RICHARD

    IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

    Abstract: The cell memory of dynamic random access type comprises a MOS (metal-oxide-silicon) transistor and a capacitor in monolithic structure with the second electrode (311) common to all cells of the same row covered with an insulating layer (312), and comprising independent conducting elements (313-1,313-2) mutually spaced in the same horizontal plane and alternatively high and low polarized. The low potential is the reference potential of the memory circuit equal to e.g. that of the ground. The high potential is the writing potential equal to e.g. the supply potential Vdd. The second electrode (311) is made up of a metallic layer of e.g. tungsten, and a conducting layer of e.g. polycrystalline silicon. The insulating layer (312) is of e.g. silicon oxide. The equivalent capacitance of the memory circuit is in the form of three decoupling capacitors connected in a triangle; the first and second capacitors are formed between the second electrode (311) and the first and the second conducting elements, respectively; the third capacitor is formed between the first and the second elements (313-1) and (313-2). In the case of the conducting elements with a surface of size 1.55 micrometer by 2.8 micrometer, and the insulating layer of thickness 9 micrometer, the three capacitances are: 145 pF, 166 pF, and 166 pF.

    69.
    发明专利
    未知

    公开(公告)号：DE69923900D1

    公开(公告)日：2005-04-07

    申请号：DE69923900

    申请日：1999-09-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

    Abstract: The memory realized in an integrated circuit chip (2') comprises a matrix network of cells divided in sections (S), rows of amplifiers for column decoding (CDEC) with outputs interconnected to decoded bit lines, each comprising two perpendicular sections, one in the row direction for connecting directly each decoded bit line to the input/output (I/O) stage at the extremity of rows. The circuits for row decoding (RDEC), predecoding (PREDEC), input/output (I/O), and control (CONTROL) are located in the same section as the bus for address (ADD), data (DATA) and control (CTR) signals. The change of direction within two sections of the bit line is carried out without active element, by direct interconnection. The memory cell contains a transistor connected to a capacitor, and the amplifier for column decoding is directly connected to the local bit line interconnecting the drains of transistors in the same section. The circuits (PREDEC, RDEC, I/O) can be located on both sides of the integrated circuit chip. The number of rows of memory cells per section is selected to have the signal/noise ratio higher than 1/10 at inputs of amplifiers for column decoding.

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