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    65.
    发明专利
    未知

    公开(公告)号：DE69626815D1

    公开(公告)日：2003-04-24

    申请号：DE69626815

    申请日：1996-09-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10 ,  G11C7/00

    Abstract: The invention relates to a control circuit (1) for an output buffer, of the type which comprises a first input terminal (I1) receiving a first enable signal (OEn) and a second input terminal (I2) receiving a second enable signal (CEn), as well as first (O1) and second (O2) output terminals to generate first (OE_L) and second (OE_H) partial enable signals to transfer discrete sets of data bits, the first (I1) and second (I2) input terminals being coupled to the first (O1) and second (O2) output terminals through a multiplexer (2), the control circuit (1) comprising a synchronization circuit (7) for linking the partial enable signals (OE_L,OE_H) operatively to a synchronization signal (SYNC) of the pulse type being synchronous with the loading of the output buffer, the synchronization circuit (7) being connected between an output terminal (O3) of said multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1).

    66.
    发明专利
    未知

    公开(公告)号：IT1313853B1

    公开(公告)日：2002-09-24

    申请号：ITMI992480

    申请日：1999-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10

    Abstract: An output buffer, particularly for non-volatile memories, includes a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage. More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage. The first and second circuits for disabling the push-pull stage may be respectively connected between the first and second activation paths and the first data latch circuit and may receive as inputs an output enable signal and a data updating signal. Additionally, the second and third data latch circuits may be connected between the push-pull stage and, respectively, the first and second activation paths for the activation of the push-pull stage.

    67.
    发明专利
    未知

    公开(公告)号：DE69617919T2

    公开(公告)日：2002-08-08

    申请号：DE69617919

    申请日：1996-06-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C29/00 ,  G11C29/24 ,  G06F11/20

    Abstract: A semiconductor memory device comprising redundancy memory elements for functionally replacing defective memory elements, redundancy circuits (6,7) for operating said functional substitution of the redundancy memory elements for the defective memory elements, and operation mode control circuits (13) for controlling the memory device to operate accoriding to a plurality of operation modes, said plurality of operation modes comprising a memory read mode and redundancy test modes for testing the redundancy circuits. The memory device comprises an internal shared bus (IB) of signal lines that when the memory device is operated in said read mode is used to transfer read data signals (RDAT) to output terminals (OB,I/O) of the memory device and when the memory device is operated in one of said redundancy test modes is used to transfer redundancy signals (RCOL,RROW,RCNT,FTS), depending on the redundancy test mode, to the output terminals of the memory device.

    68.
    发明专利
    未知

    公开(公告)号：DE69616019T2

    公开(公告)日：2002-06-06

    申请号：DE69616019

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: H02M3/07

    Abstract: A voltage booster stage (2) including a voltage booster circuit (10); a generating circuit (12) generating an enabling signal (LSP) enabling the voltage booster circuit; and a control circuit (14) controlling the generating circuit. The control circuit (14) receives a standby signal (ENB), and presents combinatorial logics (44-55) generating an operating mode signal (SPn) having a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode. The generating circuit (12) receives the operating mode signal (SPn) and the standby signal (ENB), and generates the enabling signal (LSP) enabling the voltage booster circuit in the presence of the standby signal (ENB) and the first value of the operating mode signal (SPn).

    70.
    发明专利
    未知

    公开(公告)号：ITMI20002163A1

    公开(公告)日：2002-04-08

    申请号：ITMI20002163

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10 ,  G11C16/26 ,  G11C16/32

    Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon transitions of the second type, and a fourth circuit controlled by the first circuit to supply a stimulus signal to a timing circuit of the memory, the stimulus signal corresponding to the first synchronism signal for a random-access reading, or to the second synchronism signal for a sequential reading.

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