REDUNDANT REGISTER PROGRAMMING METHOD AND COLUMN REDUNDANT INTEGRATED CIRCUIT

    公开(公告)号:JPH0822698A

    公开(公告)日:1996-01-23

    申请号:JP2664295

    申请日:1995-02-15

    Abstract: PURPOSE: To eliminate the need of generating an ON-CHIP exclusive signal to reduce the chip size by using the existing signal line in a memory to program a redundant register. CONSTITUTION: A two-dimensional array memory matrix provided with a 16-bit data bus is divided into a plurality of portions each of which is composed of a plurality of bit groups. Redundant registers RR1-4 composed of programmable non-volatile memory is capable of programming an address of the defective bit line received from a column address signal CABUS in its first block 1. Moreover, in the second block 2, an identification code MCS7-10 of the bit group to which a defective bit line belongs obtained from the first part R1-4 of the row address signal set RABUS. A programming selection means 6 selects the redundant register RR1-4 with the second part R5-8 of the row address signal set RABUS to store the address information of the defective bit line.

    LAYOUT OF REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY

    公开(公告)号:JPH08102527A

    公开(公告)日:1996-04-16

    申请号:JP6925895

    申请日:1995-03-28

    Abstract: PURPOSE: To provide the layout of a redundancy circuit, wherein the chip area required for realization of redundancy becomes a minimum area. CONSTITUTION: An array MAR of a programmable nonvolatile memory, which stores a redundancy bit line, a redundancy word line, a defective bit line, which should be functionally replaced respectively, and the address of a word line is provided. The layout of the redundancy circuit is divided into a plurality of the same layout strips LS1-LS4, which intersect the array at right angles and have first and second strip parts at both sides of the array. The first strip part intersects a column-address signal bus CABUS, extending in parallel with the array. The second strip part intersects a row-address signal bus (RABUS), extending in parallel with the array.

    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT

    公开(公告)号:JPH0855485A

    公开(公告)日:1996-02-27

    申请号:JP4796295

    申请日:1995-02-14

    Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

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