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公开(公告)号:JP2682502B2
公开(公告)日:1997-11-26
申请号:JP5377695
申请日:1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , MACCARRONE MARCO , OLIVO MARCO
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公开(公告)号:JP2599579B2
公开(公告)日:1997-04-09
申请号:JP6925895
申请日:1995-03-28
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , CARRERA MARCELLO , DEFENDI MARCO
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公开(公告)号:JPH0822698A
公开(公告)日:1996-01-23
申请号:JP2664295
申请日:1995-02-15
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , OLIVO MARCO
IPC: G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
Abstract: PURPOSE: To eliminate the need of generating an ON-CHIP exclusive signal to reduce the chip size by using the existing signal line in a memory to program a redundant register. CONSTITUTION: A two-dimensional array memory matrix provided with a 16-bit data bus is divided into a plurality of portions each of which is composed of a plurality of bit groups. Redundant registers RR1-4 composed of programmable non-volatile memory is capable of programming an address of the defective bit line received from a column address signal CABUS in its first block 1. Moreover, in the second block 2, an identification code MCS7-10 of the bit group to which a defective bit line belongs obtained from the first part R1-4 of the row address signal set RABUS. A programming selection means 6 selects the redundant register RR1-4 with the second part R5-8 of the row address signal set RABUS to store the address information of the defective bit line.
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公开(公告)号:JP2674550B2
公开(公告)日:1997-11-12
申请号:JP4796295
申请日:1995-02-14
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
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公开(公告)号:JP2591922B2
公开(公告)日:1997-03-19
申请号:JP30490094
申请日:1994-12-08
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , MACCARRONE MARCO
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公开(公告)号:JPH08102527A
公开(公告)日:1996-04-16
申请号:JP6925895
申请日:1995-03-28
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , CARRERA MARCELLO , DEFENDI MARCO
IPC: G11C17/00 , G11C5/02 , G11C16/06 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/10
Abstract: PURPOSE: To provide the layout of a redundancy circuit, wherein the chip area required for realization of redundancy becomes a minimum area. CONSTITUTION: An array MAR of a programmable nonvolatile memory, which stores a redundancy bit line, a redundancy word line, a defective bit line, which should be functionally replaced respectively, and the address of a word line is provided. The layout of the redundancy circuit is divided into a plurality of the same layout strips LS1-LS4, which intersect the array at right angles and have first and second strip parts at both sides of the array. The first strip part intersects a column-address signal bus CABUS, extending in parallel with the array. The second strip part intersects a row-address signal bus (RABUS), extending in parallel with the array.
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公开(公告)号:JPH0855485A
公开(公告)日:1996-02-27
申请号:JP4796295
申请日:1995-02-14
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.
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公开(公告)号:JP2001243778A
公开(公告)日:2001-09-07
申请号:JP2001022134
申请日:2001-01-30
Applicant: ST MICROELECTRONICS SRL
Inventor: CAMPANALE FABRIZIO , TOMAIUOLO FRANCESCO , NICOSIA SALVATORE , DE AMBROGGI LUCA GIUSEPPE , KUMAR PROMOD , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To provide a multi-purpose memory device suitable for an application example of a wider range independently of whether reading of data is required or not in the asynchronous mode (as in standard memory) in random access or in a synchronous progressive mode in burst type access. SOLUTION: A memory device recognizes modes of access and reading required by a microprocessor, also enables performing self-conditioning of its internal circuit based on such a recognition to perform reading data in a required mode. At the time, an additional external control signal is not required, and sacrifice is not forced in an access time and a reading time as compared with obtained one in the case of a memory device constituted specifically for any one of operation modes for constitution of the same manufacturing technology and conventional technology.
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公开(公告)号:JP2791285B2
公开(公告)日:1998-08-27
申请号:JP29488194
申请日:1994-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , PADOAN SILVIA
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公开(公告)号:JP2737686B2
公开(公告)日:1998-04-08
申请号:JP5377795
申请日:1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor: PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
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