公开(公告)号：US20180145212A1

公开(公告)日：2018-05-24

申请号：US15857872

申请日：2017-12-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Rakesh Jain ,  Michael Shur

IPC: H01L33/10 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/46 ,  H01S5/022

CPC classification number: H01L33/10 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/32 ,  H01L33/46 ,  H01S5/0224

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.

公开(公告)号：US09831382B2

公开(公告)日：2017-11-28

申请号：US13692191

申请日：2012-12-03

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L21/02 ,  H01L29/15 ,  H01L33/06 ,  H01L33/00 ,  H01L33/02

CPC classification number: H01L33/06 ,  H01L21/0237 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/151 ,  H01L33/007 ,  H01L33/025

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

公开(公告)号：US09818826B2

公开(公告)日：2017-11-14

申请号：US14519230

申请日：2014-10-21

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L33/00 ,  H01L33/12 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/151 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0075 ,  H01L33/12

Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

公开(公告)号：US09806228B2

公开(公告)日：2017-10-31

申请号：US15389479

申请日：2016-12-23

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L27/15 ,  H01L31/072 ,  H01L33/06 ,  H01L33/32 ,  H01L33/24 ,  H01L33/12 ,  H01L21/02 ,  H01L29/778 ,  H01L33/22 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L33/06 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/7786 ,  H01L33/12 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09748440B2

公开(公告)日：2017-08-29

申请号：US15225382

申请日：2016-08-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Jinwei Yang ,  Remigijus Gaska ,  Mikhail Gaevski

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/18 ,  H01L33/38 ,  H01S5/022 ,  H01L33/30 ,  H01S5/343 ,  H01S5/32 ,  H01S5/34

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/18 ,  H01L33/30 ,  H01L33/382 ,  H01L2224/14 ,  H01S5/0224 ,  H01S5/3209 ,  H01S5/3413 ,  H01S5/34333

Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

公开(公告)号：US20170229612A1

公开(公告)日：2017-08-10

申请号：US15495192

申请日：2017-04-24

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/32 ,  H01L33/24 ,  H01L33/10 ,  H01L33/06 ,  H01L33/12 ,  H01L33/00

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  Y02P90/265

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

公开(公告)号：US09691939B2

公开(公告)日：2017-06-27

申请号：US14822508

申请日：2015-08-10

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L33/22 ,  H01L33/32 ,  H01L33/24 ,  H01L21/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L33/12 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/06 ,  H01L33/10 ,  H01L33/145 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L33/405 ,  H01L2933/0091

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

公开(公告)号：US20170179335A1

公开(公告)日：2017-06-22

申请号：US15391948

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L29/66 ,  H01L29/778 ,  H01L33/32 ,  H01L33/12

CPC classification number: H01L33/0025 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

公开(公告)号：US09653313B2

公开(公告)日：2017-05-16

申请号：US15144064

申请日：2016-05-02

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L31/0256 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L33/00 ,  H01L33/12

CPC classification number: H01L21/308 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/158 ,  H01L29/2003 ,  H01L29/66075 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US20170005228A1

公开(公告)日：2017-01-05

申请号：US15265975

申请日：2016-09-15

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L33/06 ,  H01L29/15 ,  H01L33/00 ,  H01L29/20 ,  H01L33/32 ,  H01L21/02

CPC classification number: H01L33/12 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/155 ,  H01L29/2003 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

Abstract translation: 提供了用于制造光电子器件的异质结构。 异质结构包括诸如n型接触或包覆层的层，其包括插入其中的薄子层。 薄的子层可以遍及整个层间隔开，并由用于该层的材料制成的中间子层隔开。 薄的子层可以具有与插入的子层不同的组成，其在异质结构的生长期间改变应力存在。