X-RAY SENSOR AND SIGNAL PROCESSING ASSEMBLY FOR AN X-RAY COMPUTED TOMOGRAPHY MACHINE
    63.
    发明申请
    X-RAY SENSOR AND SIGNAL PROCESSING ASSEMBLY FOR AN X-RAY COMPUTED TOMOGRAPHY MACHINE 有权
    X射线计算机成像机的X射线传感器和信号处理装置

    公开(公告)号:US20140270057A1

    公开(公告)日:2014-09-18

    申请号:US14187905

    申请日:2014-02-24

    Abstract: An apparatus having an X-ray sensor assembly with X-ray blocking pixels divided by X-ray transmitting gaps with the X-ray blocking pixels casting an X-ray blocking shadow; and a die containing signal processing electronics, with the signal processing electronics positioned substantially entirely within the X-ray blocking shadow. A method for detecting the alignment between the X-ray sensor assembly and the die is disclosed. Also disclosed is an X-ray computed tomography machine having a printed circuit board (“PCB”), a die embedded in the PCB, and a signal source wherein signals are routed to and from the die by traces on at least one of the surfaces of the PCB.

    Abstract translation: 一种具有X射线遮挡像素的X射线传感器组件的X射线传感器组件的装置,X射线遮挡像素被X射线透射间隙除以X射线遮挡像素投射X射线遮挡阴影; 以及包含信号处理电子器件的管芯,信号处理电子器件基本上完全位于X射线阻挡阴影内。 公开了一种用于检测X射线传感器组件和模具之间的对准的方法。 还公开了一种X射线计算机断层摄影机,其具有印刷电路板(“PCB”),嵌入在PCB中的管芯,以及信号源,其中信号通过至少一个表面上的迹线被引导到管芯和从管芯 的PCB。

    Printed package and method of making the same

    公开(公告)号:US12230594B2

    公开(公告)日:2025-02-18

    申请号:US17557372

    申请日:2021-12-21

    Abstract: A method for interconnecting bond pads of semiconductor dies or devices with corresponding leads in a lead frame with printed conductive interconnects in lieu of bond wires and an apparatus resulting from the above method. More specifically, some examples include printing an insulating foundation path from bond-pads on a semiconductor die to leads of a lead frame to which the semiconductor die is attached. A foundation conductive trace is printed on top of the insulating foundation path from each bond pad on the die to a corresponding lead of the lead frame. Optionally, on top of the conductive trace, a cover insulating cover layer is applied on exposed portions of the conductive interconnects and the foundation insulating layer. Preferably, this can be the same material as foundation layer to fully adhere and blend into a monolithic structure, rather than separate layers. Optionally, a protective layer is then applied on the resulting apparatus.

    Leadframes in semiconductor devices

    公开(公告)号:US12183703B2

    公开(公告)日:2024-12-31

    申请号:US17505494

    申请日:2021-10-19

    Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

    INTEGRATED CIRCUIT PACKAGE WITH CURRENT SENSE ELEMENT

    公开(公告)号:US20240369598A1

    公开(公告)日:2024-11-07

    申请号:US18773506

    申请日:2024-07-15

    Abstract: A semiconductor device includes a leadframe having a first level and a second level. The semiconductor device includes a semiconductor die and a conductive alloy. The conductive alloy is between the semiconductor die and the first level of the lead frame. The conductive alloy is configured to be a current sense element. The semiconductor device further includes a first conductive post coupling the semiconductor die to the conductive alloy, a second conductive post coupling the semiconductor die to the conductive alloy, and a third conductive post coupling the semiconductor die to the second level of the lead frame. The second conductive post is configured to be a first sense terminal. The third conductive post is configured to be a second sense terminal.

    Integrated capacitor with extended head bump bond pillar

    公开(公告)号:US11810843B2

    公开(公告)日:2023-11-07

    申请号:US17404970

    申请日:2021-08-17

    Abstract: A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die.

    Lidar imaging receiver
    68.
    发明授权

    公开(公告)号:US11573324B2

    公开(公告)日:2023-02-07

    申请号:US16203170

    申请日:2018-11-28

    Abstract: Described examples include a receiver having a beam splitter arranged to receive reflected light from a scene illuminated by a transmitted light signal, the beam splitter structured to provide at least two copies of the reflected light including at least two regions having sub-regions, wherein the sub-regions are not adjacent to each other. The receiver also includes a first sensor array arranged to receive one region of the reflected light and provide an output representative of that region of the reflected light. The receiver also includes a second sensor array arranged to receive the other region of the reflected light and provide a second output representative of the second region of the reflected light. The receiver also includes a combiner arranged to receive the outputs of the sensor arrays to provide a combined representation of the reflected light.

    Leadframes in Semiconductor Devices

    公开(公告)号:US20220037277A1

    公开(公告)日:2022-02-03

    申请号:US17505494

    申请日:2021-10-19

    Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

    Packaged device with die wrapped by a substrate

    公开(公告)号:US11201096B2

    公开(公告)日:2021-12-14

    申请号:US16506526

    申请日:2019-07-09

    Abstract: A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads.

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