公开(公告)号：US20220085283A1

公开(公告)日：2022-03-17

申请号：US17533003

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US20220084878A1

公开(公告)日：2022-03-17

申请号：US17023391

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105

Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

公开(公告)号：US11211471B1

公开(公告)日：2021-12-28

申请号：US17017666

申请日：2020-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ji-Min Lin ,  Ching-Yang Chuang ,  Kun-Ju Li

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

公开(公告)号：US11145602B2

公开(公告)日：2021-10-12

申请号：US16786919

申请日：2020-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

IPC: H01L23/544 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

公开(公告)号：US11004897B2

公开(公告)日：2021-05-11

申请号：US16531108

申请日：2019-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US10446745B1

公开(公告)日：2019-10-15

申请号：US16004446

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Kun-Ju Li

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L27/12

Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.

公开(公告)号：US20180061656A1

公开(公告)日：2018-03-01

申请号：US15245194

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

公开(公告)号：US09875909B1

公开(公告)日：2018-01-23

申请号：US15220365

申请日：2016-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/321 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/302 ,  H01L21/306

CPC classification number: H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US20170047251A1

公开(公告)日：2017-02-16

申请号：US14824091

申请日：2015-08-12

Applicant: United Microelectronics Corp.

Inventor： Yi-Hui Lee ,  Kun-Ju Li ,  Wei-Cyuan Lo ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract translation: 一种制造半导体器件的方法包括：提供具有有源区的半导体; 在半导体上沉积介电层; 在介电层上形成图案化的蚀刻掩模; 在介电层和图案化的蚀刻掩模上沉积另外的介电层; 平面化另外的介电层，直到图案化的蚀刻掩模曝光; 以及形成另一图案化的蚀刻掩模，其在所述另外的电介质层上具有开口，使得所述图案化蚀刻掩模的部分从所述开口露出。

公开(公告)号：US20170040435A1

公开(公告)日：2017-02-09

申请号：US14840041

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC: H01L29/66 ,  H01L29/49 ,  C22C32/00 ,  H01L29/423

CPC classification number: H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底和衬底上的栅极结构。 栅极结构包括在衬底上的高k电介质层和高k电介质层上的底部阻挡金属（BBM）层。 优选地，BBM层包括顶部，中间部分和底部，其中顶部是富氮部分，中部和底部是富钛部分。