Digital to analogue conversion
    61.
    发明专利

    公开(公告)号:GB2507096A

    公开(公告)日:2014-04-23

    申请号:GB201218794

    申请日:2012-10-19

    Inventor: LESSO JOHN PAUL

    Abstract: A digital to analogue conversion (DAC) circuit is disclosed having dynamic gain control which acts to make better use of the input range of DAC 101. A gain controller 201 has a gain allocation module 204 for controlling the allocation of gain between a digital variable gain (scaling) unit 102 and an analogue variable gain element 103 in response to changes in signal level in the input digital audio signal DIN. The digital variable gain element 102 applies gain (scaling) to the input digital signal upstream of a DAC 101 and the analogue variable gain element 103 applies a compensating analogue gain. In the present invention the gain allocation module is operable in first and second modes of operation where the response to reductions in signal level is slower in the first mode than in the second mode of operation. A low-level detector 202 monitors the input digital audio signal so as to detect a low-level part of the signal and the gain controller changes from the first mode to the second mode following detection of a low-level part of the input digital audio signal. The response of the gain allocation module in the second mode is preferably sufficiently fast to allow the digital gain to be changed to a target setting suitable for the low-level part of the signal before it is received at the digital gain element.

    DC OFFSET COMPENSATION
    63.
    发明专利

    公开(公告)号:HK1171119A1

    公开(公告)日:2013-03-15

    申请号:HK12111731

    申请日:2012-11-19

    Inventor: LESSO JOHN PAUL

    Abstract: An apparatus and method for DC offset compensation. An amplifier receives an input signal (AIN) and provides an amplified output signal (SOUT) and a feedback path provides DC offset compensation. The feedback path comprises at least one voltage controlled oscillator (VCO) and a counter. The VCO provides, over time, a first VCO output signal based on said amplified output signal and a second VCO output signal based on a reference signal (VREF). The counter generates first pulse counts based upon the first VCO output signal and second pulse counts based upon the second VCO output signal and provides a compensation signal based on a comparison of the first and second pulse counts. One voltage controlled oscillator may sequentially receive a signal based on said amplifier output signal and the reference signal from a multiplexer so as to sequentially produce the first and second VCO output signals.

    Amplifier circuit
    64.
    发明专利

    公开(公告)号:GB2451528B

    公开(公告)日:2012-10-17

    申请号:GB0716923

    申请日:2007-08-30

    Inventor: LESSO JOHN PAUL

    Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.

    DC-DC converter circuit which overcomes the problem of stressing switches

    公开(公告)号:GB2479445A

    公开(公告)日:2011-10-12

    申请号:GB201105775

    申请日:2006-08-31

    Abstract: In a dc-dc converter circuit for generating a split rail (dual polarity), supply, electrical power from an input voltage supply V1 is converted to first and second output voltages V2+, V2- of opposite polarities using a single inductor L and only four principal switches S1, S2, S4, S6. In contrast to known circuits, none of the switches S1, S2, S4, S6 is exposed to voltages greater than the input voltage V1. In a first type of charging cycle (Fig. 5(a)-(c)), the first output voltage V2+ is obtained from the input voltage supply V1 through the inductor L, in a second type of charging cycle (Fig. 5 (d)-(f)), the second output voltage V2-is obtained from the first output voltage V1 via the intermediate step of storing energy in the same inductor L as is used in the first type of charging cycle. Auxiliary switches S7a, S7b can be operated in wait states between cycles of the first and second type. The invention is of particular use in an audio amplifier.

    Charge pump circuit and methods of operation thereof

    公开(公告)号:GB2444985B

    公开(公告)日:2011-09-14

    申请号:GB0625956

    申请日:2006-12-22

    Inventor: LESSO JOHN PAUL

    Abstract: A charge pump circuit, and associated method and apparatuses, for providing a split-rail voltage supply, the circuit having a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of said states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

    Charge pump circuit with dual rail output

    公开(公告)号:GB2478458A

    公开(公告)日:2011-09-07

    申请号:GB201108798

    申请日:2006-12-22

    Inventor: LESSO JOHN PAUL

    Abstract: A charge pump circuit for providing a split-rail voltage supply is disclosed. The circuit comprises first and second flying capacitors Cf1, Cf2 and a network of switches S1 - S8 that is operable in a number of different states. A controller 420 operates the switches in a sequence of states so as to generate positive and negative output voltages Vout+, Vout- together spanning a voltage approximately equal to the input voltage +Vdd and centred on the voltage at the common terminal N11.

    Charge pump circuit with dual rail output

    公开(公告)号:GB2478457A

    公开(公告)日:2011-09-07

    申请号:GB201108796

    申请日:2006-12-22

    Inventor: LESSO JOHN PAUL

    Abstract: A charge pump circuit for providing a split-rail voltage supply is disclosed. The circuit comprises first and second flying capacitors Cf1, Cf2 and a network of switches S1 - S8 that is operable in a number of different states. A controller 420 operates the switches in a sequence of states so as to generate positive and negative output voltages Vout+, Vout- together spanning a voltage approximately equal to the input voltage +Vdd and centred on the voltage at the common terminal N11.

    Charge pump circuit and methods of operation thereof

    公开(公告)号:GB2447426B

    公开(公告)日:2011-07-13

    申请号:GB0625957

    申请日:2006-12-22

    Abstract: A charge pump circuit and associated method and apparatuses for providing a plurality of output voltages using a single flying capacitor. The circuit includes a network of switches that are operable in a number of different states and a controller for operating the switches in a sequence of states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

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