CIRCUIT FOR DELAYING ANALOG SIGNAL
    61.
    发明专利

    公开(公告)号:JP2003158444A

    公开(公告)日:2003-05-30

    申请号:JP2002322844

    申请日:2002-11-06

    Applicant: YAMAHA CORP

    Abstract: PROBLEM TO BE SOLVED: To reduce the influence of the parasitic capacitance Cp of an output line Lout in reading from memory cells M1 to Mn. SOLUTION: An operational amplifier 40 for performing negative-feedback output of the voltage of the output line Lout of the memory cells M1 to Mn through a capacitor Cs, and a switch SW0 connected to the capacitor Cs in parallel are provided. Before a reading operation from the memory cells M1 to Mn, the switch SW0 is turned on, the output line Lout is virtually grounded, and electric charge stored in the capacitor Cs is also cleared. If the witch SW0 is turned off and any of the memory cells is connected to the output line Lout that is virtually grounded, the electric charge stored in the memory cell moves to the capacitor Cs without being affected by the parasitic capacitance Cp.

    D/A CONVERTER
    62.
    发明专利

    公开(公告)号:JPH0946230A

    公开(公告)日:1997-02-14

    申请号:JP21098595

    申请日:1995-07-27

    Applicant: YAMAHA CORP

    Inventor: MAEJIMA TOSHIO

    Abstract: PROBLEM TO BE SOLVED: To constitute a D/A converter to be compact without the increase of elements owing to multiple bits. SOLUTION: Voltage sources V1 and V2 are prepared in accordance with '0' and '1' of digital input. A capacitor C1 is connected to the sources through transfer gates TG1 and TG2. A capacitor C2 is connected to the capacitor C1 through a transfer gate TG3. A charge-voltage conversion circuit 1 is connected to the terminal of the capacitor C2 through a transfer gate TG4 and a sample-and-hold circuit 2 is connected to the output. A clock generation circuit 3 generating control clocks driving the transfer gates TG1-TG4 in synchronizing with respective bit data of digital data which are supplied from LSB in order is provided. The charging of C1 by V1 and V2 responding to bit data from LSB and charge distribution between C1 and C2 are repeated and the charge quantity of C2 is voltage-converted so as to obtain analog output.

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