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    Electrochemical cobalt silicide liner for metal contact fills and damascene processes
    61.
    发明授权
    Electrochemical cobalt silicide liner for metal contact fills and damascene processes 有权
    用于金属接触填充和镶嵌工艺的电化学钴硅化物衬垫

    公开(公告)号：US06420784B2

    公开(公告)日：2002-07-16

    申请号：US09740189

    申请日：2000-12-19

    Applicant: Yongjun Jeff Hu ,  Li Li

    Inventor： Yongjun Jeff Hu ,  Li Li

    IPC: H01L2348

    CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868

    Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

    Abstract translation: 公开了衬垫材料和使用方法。 该方法包括将硅层沉积到诸如通路或沟槽的深空隙中，并将钴种子层物理气相沉积到硅上。 辅助钴层在种子层上电镀。 然后将该结构退火，形成硅化钴（CoSix）。 该层可以制成非常薄，便于用高导电性金属进一步填充通孔。 有利地，该层没有氧气和氮气，因此允许低温金属回流填充通孔。 衬垫材料在各种集成电路金属化工艺中具有特殊的用途，例如镶嵌和双镶嵌工艺。

    Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
    62.
    发明授权
    Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line 有权
    形成高纯度<200>晶粒取向锡层的半导体加工方法和形成导电互连线的半导体加工方法

    公开(公告)号：US6100185A

    公开(公告)日：2000-08-08

    申请号：US134624

    申请日：1998-08-14

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11 ,  H01L21/4763

    CPC classification number: H01L27/1104 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/76895

    Abstract: Conductive structures, conductive lines, conductive SRAM lines, integrated circuitry, SRAM cells, and methods of forming the same are described. In one embodiment, a substrate is provided and a layer comprising TiN is physical vapor deposited over the substrate having greater than or equal to about 90% by volume grain orientation. In another embodiment, at least two components are electrically connected by forming a layer of TiN over a substrate having the desired by-volume concentration of grain orientation, and etching the layer to form a conductive line. In a preferred embodiment, conductive lines formed in accordance with the invention electrically connect at least two SRAM components and preferably form cross-coupling electrical interconnections between first and second inverters of an SRAM cell.

    Abstract translation: 介绍导电结构，导线，导电SRAM线，集成电路，SRAM单元及其形成方法。 在一个实施例中，提供基底，并且包含TiN的层在物理上蒸镀在基底上，具有大于或等于约90％（体积）的晶粒取向。 在另一个实施方案中，至少两个组分通过在具有所需体积浓度<200>晶粒取向的衬底上形成TiN层而电连接，并蚀刻该层以形成导电线。 在优选实施例中，根据本发明形成的导线电连接至少两个SRAM组件，并且优选地在SRAM单元的第一和第二反相器之间形成交叉耦合电互连。

    Semiconductor processing methods, and methods of forming isolation structures
    63.
    发明授权
    Semiconductor processing methods, and methods of forming isolation structures 有权
    半导体加工方法和形成隔离结构的方法

    公开(公告)号：US08906771B2

    公开(公告)日：2014-12-09

    申请号：US13603100

    申请日：2012-09-04

    Applicant: Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    Inventor： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    Abstract translation: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

    Semiconductor constructions
    64.
    发明授权
    Semiconductor constructions 失效
    半导体结构

    公开(公告)号：US08274081B2

    公开(公告)日：2012-09-25

    申请号：US12728942

    申请日：2010-03-22

    Applicant: Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    Inventor： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    IPC: H01L29/04 ,  H01L33/16

    CPC classification number: H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    Abstract translation: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

    Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Isolation Structures
    67.
    发明申请
    Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Isolation Structures 失效
    半导体结构，半导体加工方法和形成隔离结构的方法

    公开(公告)号：US20110227071A1

    公开(公告)日：2011-09-22

    申请号：US12728942

    申请日：2010-03-22

    Applicant: Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    Inventor： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/22 ,  H01L21/336

    CPC classification number: H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    Abstract translation: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

    Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units
    68.
    发明申请
    Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units 有权
    半导体结构，形成晶体管门的方法和形成NAND单元的方法

    公开(公告)号：US20090294831A1

    公开(公告)日：2009-12-03

    申请号：US12128404

    申请日：2008-05-28

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/792 ,  H01L21/4763

    CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中公共处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

    Word lines for memory cells
    69.
    发明授权
    Word lines for memory cells 有权
    记忆单元的字线

    公开(公告)号：US07545009B2

    公开(公告)日：2009-06-09

    申请号：US11072159

    申请日：2005-03-04

    Applicant: Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

    Inventor： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

    IPC: H01L29/78

    CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

    Abstract translation: 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

    Electrically Conductive Line
    70.
    发明申请
    Electrically Conductive Line 审中-公开
    导电线

    公开(公告)号：US20080284025A1

    公开(公告)日：2008-11-20

    申请号：US12173483

    申请日：2008-07-15

    Applicant: Qi Pan ,  Jiutao Li ,  Yongjun Jeff Hu ,  Allen McTeer

    Inventor： Qi Pan ,  Jiutao Li ,  Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L23/52

    CPC classification number: H01L21/76838 ,  H01L21/28061 ,  H01L21/28518 ,  H01L21/2855 ,  H01L23/485 ,  H01L27/10891 ,  H01L29/4933 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0. The silicon-comprising layer, the electrically conductive layer, the MSixNy-comprising layer, the MSiz-comprising layer, and the TiSia-comprising layer are patterned into a stack comprising an electrically conductive line. Other aspects and implementations are contemplated.

    Abstract translation: 本发明包括导电线，形成导电线的方法，以及在多晶硅晶体管栅极线上制造钛硅化物时还原钛硅化物聚集的方法。 在一个实施方案中，形成导电线的方法包括在衬底上提供含硅层。 在含硅层之上形成导电层。 在导电层上方形成了一个MSi x N N y S y - 含量，其中“x”为0至3.0，“y”为0.5至10，以及 “M”是Ta，Hf，Mo和W中的至少一种。在MSi x N y y上，形成MSiZb含量层。 其中“z”为1〜3.0。 在MSiZ包含层上形成TiSi 1 a含量层，其中“a”为1至3.0。 包含硅的层，导电层，包含MSi x N的混合层，包含MSi的混合层和 将TiSi 1 a含有层图案化成包括导电线的堆叠。 考虑了其他方面和实现。

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