公开(公告)号：WO2008110854A2

公开(公告)日：2008-09-18

申请号：PCT/IB2007/000629

申请日：2007-03-14

Applicant: STMICROELECTRONICS S.R.L. ,  SITI, Massimiliano

Inventor： SITI, Massimiliano

IPC: H04L25/03 ,  H04L27/26

CPC classification number: H04L25/03318 ,  H04L1/005 ,  H04L25/03006 ,  H04L27/2601 ,  H04L2025/03426

公开(公告)号：WO2008089969A2

公开(公告)日：2008-07-31

申请号：PCT/EP2008/000495

申请日：2008-01-23

Applicant: STMICROELECTRONICS S.R.L. ,  BALDO, Lorenzo ,  COMBI, Chantal ,  CORTESE, Mario, Francesco

Inventor： BALDO, Lorenzo ,  COMBI, Chantal ,  CORTESE, Mario, Francesco

IPC: B81B7/00 ,  G01L9/00 ,  G01L13/02 ,  G01D11/24

CPC classification number: B81B7/0061 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C2203/0154 ,  G01L19/141 ,  G01L19/147 ,  G01L19/148 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Electronic device (1, 1a, 1b, 1c, 1d, 1e) which comprises: a substrate (2) provided with at least one passing opening (5), a MEMS device (7) with function of differential sensor provided with a first and a second surface (9, 10) and of the type comprising at least one portion (11) sensitive to chemical and/or physical variations of fluids present in correspondence with a first and a second opposed active surface (11a, 11b) thereof, the first surface (9) of the MEMS device (7) leaving the first active surface (11a) exposed and the second surface (10) being provided with a further opening (12) which exposes said second opposed active surface (11b), the electronic device (1, 1d, 1e) being characterised in that the first surface (9) of the MEMS device (7) faces the substrate (2) and is spaced therefrom by a predetermined distance, the sensitive portion (11) being aligned to the passing opening (5) of the substrate (2), and in that it also comprises: a protective package (14, 14a, 14b), which incorporates at least partially the MEMS device (7) and the substrate (2) so as to leave the first and second opposed active surfaces (11a, 11b) exposed respectively through the passing opening (5) of the substrate (2) and the further opening (12) of the second surface (10).

Abstract translation: 一种电子装置（1,1a，1b，1c，1d，1e），包括：设置有至少一个通过开口（5）的衬底（2），具有功能的MEMS装置（7） ，所述差动传感器设置有第一和第二表面（9,10），并且所述类型包括至少一个对与第一和第二相对的有效表面相对应的流体的化学和/或物理变化敏感的部分（11） （11a，11b），所述MEMS器件（7）的第一表面（9）离开所述第一有源表面（11a）并且所述第二表面（10）设置有另一开口（12），所述另一开口（12）暴露所述第二对置 所述电子装置（1,1d，1e）的特征在于，所述MEMS装置（7）的所述第一表面（9）面向所述衬底（2）且与所述衬底（2）隔开预定距离，所述敏感表面 部分（11）与衬底（2）的通过开口（5）对准，并且其还包括：保护包装（14， ，其至少部分地并入MEMS器件（7）和衬底（2），从而使第一和第二相对的有源表面（11a，11b）分别暴露于衬底的通过开口（5） （2）和第二表面（10）的另一开口（12）。

公开(公告)号：WO2007148355A1

公开(公告)日：2007-12-27

申请号：PCT/IT2006/000478

申请日：2006-06-22

Applicant: STMICROELECTRONICS S.R.L. ,  PAU, Danilo ,  BORNEO, Antonio Maria ,  LAVIGNA, Daniele

Inventor： PAU, Danilo ,  BORNEO, Antonio Maria ,  LAVIGNA, Daniele

IPC: H04N7/26 ,  G06T15/00

CPC classification number: G06T9/001 ,  H04N19/27 ,  H04N19/42 ,  H04N19/436 ,  H04N19/44

Abstract: A system for decoding a stream of compressed digital video images (IS) comprises a graphics accelerator (152 to 158) for reading (152) the stream of compressed digital video images, creating (154, 156), starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting (158, 160) the three-dimensional scenes to be rendered into decoded video images (OS). The graphics accelerator (152 to 158) is preferentially configured as pipeline (102) selectively switchable between operation in a graphics context and operation for decoding the stream of video images (IS) . The graphics accelerator (152 to 158) is controllable during operation for decoding the stream of compressed digital video images (IS) via a set of Application Programmer's Interfaces (APIs) comprising, in addition to new APIs, also standard APIs for operation of the graphics, accelerator (152 to 158) in a graphics context.

Abstract translation: 用于对压缩数字视频图像（IS）流进行解码的系统包括用于读取（152）压缩数字视频图像流的图形加速器（152至158），从所述压缩数字视频图像流开始创建（154,156） 视频图像，要渲染的三维场景，以及将待渲染的三维场景转换（158,160）为解码视频图像（OS）。 图形加速器（152至158）优选地配置为在图形上下文中的操作和用于解码视频图像（IS）流的操作之间可选择地切换的流水线（102）。 图形加速器（152至158）在操作期间是可控的，用于经由一组应用程序接口（API）解码压缩数字视频图像（IS）流，除了新的API之外，还包括用于操作图形的标准API ，加速器（152至158）。

公开(公告)号：WO2007132483A1

公开(公告)日：2007-11-22

申请号：PCT/IT2006/000350

申请日：2006-05-11

Applicant: STMICROELECTRONICS S.R.L. ,  PATTI, Davide, Giuseppe ,  SETTANNI, Giuditta

Inventor： PATTI, Davide, Giuseppe ,  SETTANNI, Giuditta

IPC: H01L29/739 ,  H01L21/331 ,  H01L29/10

CPC classification number: H01L29/66333 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/7395

Abstract: An IGBT transistor includes a drift region (103) , at least one body region (112) housed in the drift region (103) and having a first type of conductivity, and a conduction region (124) , which crosses the body region (112) in a direction perpendicular to a surface (103a) of the drift region (103) and has the first type of conductivity and a lower resistance than the body region (112) . The conduction region (124) includes a plurality of implant regions (121, 123a-123d) , arranged at respective depths (D1-D4) from the surface (103a) of the drift region (103) .

Abstract translation: IGBT晶体管包括漂移区（103），容纳在漂移区（103）中并且具有第一类型导电性的至少一个体区（112）和穿过体区（112）的导电区域（124） ）在垂直于漂移区域（103）的表面（103a）的方向上具有比身体区域（112）低的第一类型的导电性和较低的电阻。 导电区域（124）包括从漂移区域（103）的表面（103a）相应的深度（D1-D4）排列的多个注入区域（121,123a-123d）。

公开(公告)号：WO2007108015A1

公开(公告)日：2007-09-27

申请号：PCT/IT2006/000166

申请日：2006-03-17

Applicant: STMicroelectronics S.r.l. ,  DORA S.p.A ,  CAPPELLETTI Roberto ,  CANTONE Giuseppe ,  ANTONELLI Barbara ,  CASTIGLIOLA Antonello ,  LASCIANDARE Alessandro ,  MARANO Vincenzo

Inventor： CAPPELLETTI Roberto ,  CANTONE Giuseppe ,  ANTONELLI Barbara ,  CASTIGLIOLA Antonello ,  LASCIANDARE Alessandro ,  MARANO Vincenzo

IPC: H04B3/54

CPC classification number: H04B3/54 ,  H04B2203/5416 ,  H04B2203/5425 ,  H04B2203/5433 ,  H04B2203/5458 ,  H04B2203/5491

Abstract: The invention relates to an electronic synchronous/ asynchronous transceiver device (100) for power line communication networks of the type integrated into a single chip and operating from a single supply voltage. The transceiver device includes: at least an internal register (40) that is programmable through a synchronous serial interface (41); at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier (45) with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators (30, 35) for powering with different voltage levels different kind of external controllers linked to the transceiver device (100).

Abstract translation: 本发明涉及一种用于集成到单个芯片并且从单个电源电压工作的类型的电力线通信网络的电子同步/异步收发器设备（100）。 收发器装置包括：至少一个可通过同步串行接口（41）编程的内部寄存器（40）; 至少一个线性驱动器，用于通过单端功率放大器（45）实现的电力线上的双向网络通信，其具有作为用于传输路径的可调谐有源滤波器的一部分的直接可访问输入和输出线; 以及至少一对线性调节器（30,35），用于为与所述收发器设备（100）链接的不同类型的外部控制器供电。

公开(公告)号：WO2007069281A1

公开(公告)日：2007-06-21

申请号：PCT/IT2005/000732

申请日：2005-12-13

Applicant: STMICROELECTRONICS S.R.L. ,  SCOLLO, Rosario ,  NANIA, Massimo

Inventor： SCOLLO, Rosario ,  NANIA, Massimo

IPC: H03K17/0412 ,  H03K17/567

CPC classification number: H03K17/567 ,  H03K17/0412

Abstract: The invention relates to a driving circuit (30) for an emitter-switching configuration (21) of transistors (BJT, MOS) having at least one first and one second control terminal (X1, X2) connected to the driving circuit (30) to form a controlled emitter-switching device (35) having in turn respective collector, source and gate terminals (C, S, G). Advantageously the driving circuit (30) comprises at least one IGBT device (22) inserted between the collector terminal (C) and a first end of a capacitor (C1), whose second end is connected to the first control terminal (X1), the IGBT device (22) having in turn a third control terminal (X3) connected, through a first resistive element (R1), to the gate terminal (G), as well as a second resistive element (R2) inserted between the gate terminal (G) and the second control terminal (X2). Advantageously, the driving circuit (30) further comprises an additional supply (Va) inserted between the first and second ends of the capacitor (Cl) to ensure its correct biasing.

Abstract translation: 本发明涉及一种用于晶体管（BJT，MOS）的发射极 - 开关配置（21）的驱动电路（30），其具有至少一个连接到驱动电路（30）的第一和第二控制端（X1，X2），连接到驱动电路 形成受控的发射极开关器件（35），其又具有集电极，源极和栅极端子（C，S，G）。 有利地，驱动电路（30）包括插入在集电极端子（C）和第二端连接到第一控制端子（X1）的电容器（C1）的第一端之间的至少一个IGBT器件（22）， 具有通过第一电阻元件（R1）连接到栅极端子（G）的第三控制端子（X3）的IGBT器件（22）以及插入在栅极端子（R）之间的第二电阻元件（R2） G）和第二控制端子（X2）。 有利地，驱动电路（30）还包括插入在电容器（C1）的第一和第二端之间的附加电源（Va），以确保其正确的偏置。

公开(公告)号：WO2007042336A3

公开(公告)日：2007-04-19

申请号：PCT/EP2006/064298

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02 ,  B81B7/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

公开(公告)号：WO2007006506A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006674

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10) comprising a superficial semiconductor layer (11), the method comprising the steps of: forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) carrying out at least a first ion implantation of a first type of dopant for forming at least one deep implanted region (14a); carrying out at least a second ion implantation of the first type of dopant for forming at least one body region (16) of the MOS transistor aligned with the deep implanted region (14a); the method comprising an activation thermal process with 1-14 low thermal budget of the first type and second type of dopant suitable to complete said formation of the body region (16), and of the deep implanted region (14a).

Abstract translation: 在宽带隙半导体衬底（10）上制造垂直功率MOS晶体管的方法，包括表面半导体层（11），所述方法包括以下步骤：在所述表面半导体层（11）上形成屏蔽结构（12），包括： 至少一个电介质层（12）至少执行用于形成至少一个深注入区域（14a）的第一类型掺杂剂的第一离子注入; 执行所述第一类型掺杂剂的至少第二离子注入以形成与所述深注入区域（14a）对准的所述MOS晶体管的至少一个体区（16）。 该方法包括具有适合于完成所述体区（16）的所述第一类型和第二类型掺杂物的1-14低热预算的激活热处理以及所述深注入区域（14a）。

公开(公告)号：WO2006117809A1

公开(公告)日：2006-11-09

申请号：PCT/IT2005/000258

申请日：2005-05-04

Applicant: STMICROELECTRONICS S.R.L. ,  GIUSSANI, Luca ,  SALATI, Luca

Inventor： GIUSSANI, Luca ,  SALATI, Luca

IPC: H05B41/298

CPC classification number: H05B41/2983

Abstract: The present invention refers to a driving device of a discharge lamp (10) having two cathodes. Said device comprises first means (1, 11) having a supply input voltage (Val) and suitable for providing an alternating voltage at the ends of the cathodes, second means (3) capable of monitoring a condition of each of said cathodes and suitable for measuring a first direct voltage signal (Vdc) of the waveform of the voltage of the lamp that develops when the lamp (10) approaches the ageing condition, third means (40) coupled to the second means (3) and suitable for deactivating the first means (11), fourth means (50) suitable for providing to the third means (40) a second direct voltage signal (Vdca) proportional in value to the supply voltage (Val). The third means (40) are suitable for deactivating the first means (11) when a predetermined variation of the first direct voltage signal (Vdc) occurs in relation to the second direct voltage signal (Vdca).

Abstract translation: 本发明涉及具有两个阴极的放电灯（10）的驱动装置。 所述装置包括具有电源输入电压（Val）并且适于在阴极端部提供交流电压的第一装置（1,11），能够监测每个阴极的状况并适合于 测量当灯（10）接近老化条件时产生的灯的电压的波形的第一直流电压信号（Vdc）;耦合到第二装置（3）并适于停用第一 装置（11），适于向第三装置（40）提供与电源电压（Val）成比例的第二直流电压信号（Vdca）的第四装置（50）。 当相对于第二直流电压信号（Vdca）发生第一直流电压信号（Vdc）的预定变化时，第三装置（40）适于停用第一装置（11）。

公开(公告)号：WO2006109329A1

公开(公告)日：2006-10-19

申请号：PCT/IT2005/000205

申请日：2005-04-12

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMBETTI, Osvaldo, Enrico ,  ZAFARANA, Alessandro

Inventor： ZAMBETTI, Osvaldo, Enrico ,  ZAFARANA, Alessandro

IPC: H02M3/156 ,  G05F1/565

CPC classification number: H02M3/1584 ,  H02M2001/0009

Abstract: The invention relates to a multiphase voltage regulator providing a voltage Vout to an output terminal (25) and of the type comprising N switches (3a 3b,..3n) located in parallel, providing respective current phases (Iphase1, iphase2,...IphaseN) added to each other to generate a total current (Iout) for a general load (Cout). The voltage regulator has N inductive circuits (5a 5b,..5n), each interposed between an output node (20a, 20b,..20n) of each of the N switches (3a 3b,...3n) and the output terminal (25), a sense circuit (8) which adds the voltages being in each of said output nodes (20a -20b,..20n) of said N switches (3a 3b,...3n) bringing the added voltage to an input of an amplifier circuit (10) having a second input (12) connected to the output terminal (25) to output a current (Ics) being proportional to said total current (Iout). The regulator also having a controller (15) with only two pins CS+ and CS- to read the total current (Iout), said two pins CS+ and CS- connected to the inputs of the amplifier (10).

Abstract translation: 本发明涉及向并联布置的N个开关（3a 3b，​​... 3n）的输出端（25）和包括N个开关（3a 3b，​​... 3n）的类型提供电压Vout的多相电压调节器，提供相应的电流相位（Iphase1，iphase2，...） IphaseN）相加，以产生一般负载（Cout）的总电流（Iout）。 电压调节器具有N个感应电路（5a 5b，... 5n），每个电感电路分别插入在N个开关（3a 3b，​​... 3n）中的每一个的输出节点（20a，20b，... 20n）和输出端子 （25），感测电路（8），其将所述N个开关（3a 3b，​​... 3n）的所述输出节点（20a-20b，... 20n）中的每一个中的电压相加， 具有连接到输出端子（25）的第二输入（12）的放大器电路（10），以输出与所述总电流（Iout）成比例的电流（Ics）。 调节器还具有仅具有两个引脚CS +和CS-的控制器（15）来读取总电流（Iout），所述两个引脚CS +和CS-连接到放大器（10）的输入。