公开(公告)号：WO2009079014A1

公开(公告)日：2009-06-25

申请号：PCT/US2008/013908

申请日：2008-12-18

Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE ,  YANG, Woodward ,  HYUN, Jea, Woong

Inventor： YANG, Woodward ,  HYUN, Jea, Woong

IPC: G11C16/26 ,  G11C7/10

CPC classification number: G11C16/26 ,  G11C7/1036 ,  G11C19/00

Abstract: A flash memory system may include a NAND flash memory array, and x-address circuitry configured to decode and address one or more rows of data in the NAND array. The flash memory system may further include at least one shift register configured to process the data addressed by the x-address circuitry. The flash memory system may further include at least one external clock. In some embodiments, the shift register may be an asynchronous shift register. A flash translational layer may be provided that permits multiple simultaneous data transfers.

Abstract translation: 闪速存储器系统可以包括NAND闪存阵列，以及配置成对NAND阵列中的一行或多行数据进行解码和寻址的x地址电路。 闪速存储器系统还可以包括被配置为处理由x地址电路寻址的数据的至少一个移位寄存器。 闪存系统还可以包括至少一个外部时钟。 在一些实施例中，移位寄存器可以是异步移位寄存器。 可以提供允许多次同时进行数据传输的闪存翻译层。

公开(公告)号：WO2007107182A1

公开(公告)日：2007-09-27

申请号：PCT/EP2006/060849

申请日：2006-03-17

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ,  RUTHEMANN, Klaus

Inventor： RUTHEMANN, Klaus

IPC: G11C29/02 ,  G11C7/10 ,  G11C8/06

CPC classification number: G11C7/1036 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C29/003 ,  G11C29/02

Abstract: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

Abstract translation: 一种用于调整数据存储单元的数字延迟功能的装置，包括所述数据存储单元（102），弹性存储寄存器ESR（104）和适于控制读写操作的读时钟和写时钟，写计数器 与写入时钟相关联，读取计数器与读取时钟相关联。 所述存储器（102）与所述ESR（104）串联工作。 存储器（102）从两个逻辑上相邻的单元传送两个数据元素。 所述ESR（104）在所述写入时钟的每个周期从所述存储器（102）写入所述两个数据元素，其中如果所述写入计数器在写入时钟的周期增加1，则所述存储器（102）中的输出位置是 如果写入计数器在写入时钟的一个周期增加了两个，则存储器（102）中的输出位置向后移动一个数据元素，并且如果写入计数器在写入时钟的一个周期没有改变 存储器（102）中的输出位置向前移动一个数据元素。

公开(公告)号：WO2004042506A3

公开(公告)日：2005-09-09

申请号：PCT/US0333679

申请日：2003-10-23

Applicant: RING TECHNOLOGY ENTPR LLC

Inventor： LYNCH WILLIAM T ,  HERBISON DAVID J

IPC: G06F13/16 ,  G11C7/10 ,  G11C29/12 ,  G11C5/00

CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract translation: 一种存储器访问方案，其采用串联互连的一组或多组移位寄存器，数据可以从其中加载或写入一个或多个存储器件。 也就是说，来自存储器件的数据可以被并行加载到移位寄存器组中，然后通过移位寄存器串行移位，直到从移位寄存器组输出并传送到其目的地。 此外，数据可以从/从该组移位寄存器读取和加载到存储器件中，使得在读取和/或加载数据期间移位寄存器的移位是不间断的。 此外，来自存储器件的数据可以被加载到两个或更多个并行的移位寄存器链中，然后通过移位寄存器链进行串行移位。

公开(公告)号：WO2004042506A2

公开(公告)日：2004-05-21

申请号：PCT/US2003/033679

申请日：2003-10-23

Applicant: RING TECHNOLOGY ENTERPRISES, LLC

Inventor： LYNCH, William, T. ,  HERBISON, David, J.

IPC: G06F

CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract translation: 一种存储器访问方案，其采用串联互连的一组或多组移位寄存器，数据可以从其中加载或写入一个或多个存储器件。 也就是说，来自存储器件的数据可以被并行加载到移位寄存器组中，然后通过移位寄存器串行移位，直到从移位寄存器组输出并传送到其目的地。 此外，数据可以从/从该组移位寄存器读取和加载到存储器件中，使得在读取和/或加载数据期间移位寄存器的移位是不间断的。 此外，来自存储器件的数据可以被加载到两个或更多个并行的移位寄存器链中，然后通过移位寄存器链进行串行移位。

公开(公告)号：EP3254287A1

公开(公告)日：2017-12-13

申请号：EP16746991.5

申请日：2016-01-27

Applicant: Micron Technology, Inc.

Inventor： ZAWODNY, Jason T. ,  WHEELER, Kyle B. ,  MURPHY, Richard C.

IPC: G11C7/06 ,  G11C11/413 ,  G11C11/416

CPC classification number: G06F12/0238 ,  G06F12/0888 ,  G06F15/7821 ,  G06F2212/202 ,  G06F2212/603 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

公开(公告)号：EP2577667A4

公开(公告)日：2017-05-10

申请号：EP11790301

申请日：2011-05-31

Applicant: ALTERA CORP

Inventor： FUNG RYAN ,  FENDER JOSHUA DAVID

IPC: G11C7/10 ,  G11C7/22 ,  H03K19/173

CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1093

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract translation: 一种装置包括耦合到电子设备的接口电路。 接口电路使用选通信号提供与电子设备的源同步通信。 接口电路被配置为选通选通信号以成功地与电子设备通信。

公开(公告)号：EP2446439A1

公开(公告)日：2012-05-02

申请号：EP10727608.1

申请日：2010-06-15

Applicant: SanDisk Technologies, Inc.

Inventor： CHIBVONGODZE, Hardwell ,  SAKAI, Manabu ,  KAMEI, Teruhiko

IPC: G11C7/10 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

公开(公告)号：EP1117100A1

公开(公告)日：2001-07-18

申请号：EP01300251.4

申请日：2001-01-12

Applicant: Hewlett-Packard Company, A Delaware Corporation

Inventor： Perner, Frederick A. ,  Eldredge, Kenneth J.

IPC: G11C7/10 ,  G11C19/00 ,  G11C8/00

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C19/00

Abstract: Some forms of memory data I/O require a parallel interface with the memory array and a serial interface with data ports external to the memory. A hybrid decoder/scan register data I/O (300) scheme is described that offers a high speed data access to selected points along a set of scan registers (304(1),... , 304(s)) that connect to the columns (bit lines 602) of a memory array (600). The interface to the memory array is a long register (302) which comprises a chain of scan register blocks (304). Data to and from the memory array is transferred in a parallel manner. Data I/O to a specific memory address or memory data block is routed from a serial data I/O line, through a set of switches (316) controlled by a decoder circuit (314, 320) to the input (or output) port of one of the scan register blocks (304). This hybrid data I/O circuit offers a high speed access to selected points within the column circuits of a memory array while maintaining an efficient and high speed serial output offered by a scan chain data register.

Abstract translation: 一些形式的存储器数据I / O需要与存储器阵列的并行接口以及具有存储器外部的数据端口的串行接口。 描述了混合解码器/扫描寄存器数据I / O（300）方案，其提供对沿着连接到的扫描寄存器（304（1），...，304（s））的集合的所选点的高速数据访问 存储器阵列（600）的列（位线602）。 存储器阵列的接口是长寄存器（302），其包括一串扫描寄存器块（304）。 往返于存储器阵列的数据以并行方式传送。 特定存储器地址或存储器数据块的数据I / O通过由解码器电路（314,320）控制的一组开关（314,320）从串行数据I / O线路路由到输入（或输出）端口 的一个扫描寄存器块（304）。 该混合数据I / O电路提供对存储器阵列的列电路内的选定点的高速访问，同时保持由扫描链数据寄存器提供的有效和高速的串行输出。

公开(公告)号：EP1078370A4

公开(公告)日：2001-07-04

申请号：EP99914242

申请日：1999-03-29

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/1036

Abstract: A sense amplifier (200) for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controlled manner (270), in response to a control pulse (SAEN). The control pulse (SAEN) is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps (200) are utilized to read out in parallel fashion the N memory cells (bits) comprising an accessed memory location. The sense amps (200) are therefore active only of a period of time sufficient to read out a memory cell.

Abstract translation: 响应于控制脉冲（SAEN），在串行配置存储器中使用的读出放大器（200）包括以受控方式启用和禁用（270）的多个级。 控制脉冲（SAEN）是在外部提供的时钟信号的每N个周期产生的，该时钟用于输出代表存储器装置内容的比特流。 在优选实施例中，利用N个这样的读出放大器（200）以并行方式读出包括被访问的存储器位置的N个存储器单元（位）。 因此，读出放大器（200）仅在足以读出存储单元的时间段内有效。

公开(公告)号：EP1054772A2

公开(公告)日：2000-11-29

申请号：EP99906895.0

申请日：1999-02-10

Applicant: Lexmark International, Inc.

Inventor： GIBSON, Bruce, David ,  PARISH, George, Keith

IPC: B41J1/00

CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

Abstract: An ink jet print head identification system for providing information to the electronics (98) of an ink jet printer includes a plurality of shift registers (92) having a plurality of address lines. The memory input of each shift register is electrically connected to a memory matrix that supplies digital bits of information to the shift registers (92) in response to receiving a decode input signal (94).