公开(公告)号：EP2312618A2

公开(公告)日：2011-04-20

申请号：EP10187469.1

申请日：2010-10-13

Applicant: Rohm and Haas Electronic Materials LLC

Inventor： Barr, Robert K ,  Chan, Raymond

IPC: H01L21/306 ,  H01L31/18

CPC classification number: H01L21/30604 ,  H01L21/0201 ,  H01L21/02052 ,  H01L31/18

Abstract: A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.

Abstract translation: 同时从半导体晶片清洗无机和有机污染物并微蚀刻半导体晶片的方法。 在半导体晶片从锭切割或切割之后，它们被切割流体以及来自切割过程中使用的锯的金属和金属氧化物污染。 使用含有碱性化合物和中等范围的烷氧基化物的含水碱性清洁和微蚀刻溶液来同时清洁和微蚀刻半导体晶片。

公开(公告)号：EP0525455A3

公开(公告)日：1993-09-22

申请号：EP92111576.2

申请日：1992-07-08

Applicant: SHIN-ETSU HANDOTAI COMPANY LIMITED

Inventor： Netsu, Shigeyoshi ,  Tomizawa, Shinichi

IPC: H01L21/322 ,  H01L21/304

CPC classification number: H01L21/0201 ,  H01L21/02016 ,  H01L21/3221

Abstract: A semiconductor substrate and a method of making the same are disclosed in which an inorganic protective film is formed on the back side of a silicon single crystal wafer and then a distorted layer is introduced in the back side of the wafer by sandblasting, without generating mechanical fractures on the back surface. The semiconductor substrate having such distorted layer is able to provide a long lasting extrinsic gettering effect when subjected to a high temperature heat treatment achieved when the semiconductor substrate is processed into a device.

公开(公告)号：WO2009120641A3

公开(公告)日：2009-12-10

申请号：PCT/US2009037992

申请日：2009-03-23

Applicant: APPLIED MATERIALS INC ,  PAIK YOUNG JEEN ,  BARRENTINE MELVIN ,  DESAI ABHIJIT Y ,  NGUYEN HAI ,  BHATNAGAR ASHISH ,  ALAGARSAMY RAJKUMAR

Inventor： PAIK YOUNG JEEN ,  BARRENTINE MELVIN ,  DESAI ABHIJIT Y ,  NGUYEN HAI ,  BHATNAGAR ASHISH ,  ALAGARSAMY RAJKUMAR

IPC: H01L21/304

CPC classification number: H01L21/6838 ,  B24B37/30 ,  H01L21/0201 ,  H01L21/30625 ,  Y10T428/24355 ,  Y10T428/24612

Abstract: A method and apparatus for planarizing a substrate are provided. A substrate carrier head with an improved cover for holding the substrate securely is provided. The cover may have a bead that is larger than the recess into which it fits, such that the compression forms a conformal seal inside the recess. The bead may also be left uncoated to enhance adhesion of the bead to the surface of the groove. The surface of the cover may be roughened to reduce adhesion of the substrate to the cover without using a non-stick coating.

Abstract translation: 提供了用于平坦化衬底的方法和设备。 提供具有用于牢固地保持衬底的改进的盖的衬底承载头。 盖可以具有比其适配的凹部大的凸缘，使得压缩部在凹部内形成共形密封。 珠子也可以不被涂覆以增强珠子与凹槽表面的粘附。 盖的表面可以被粗糙化以减少基材对盖的粘附而不使用不粘涂层。

公开(公告)号：WO2007062250A3

公开(公告)日：2007-08-30

申请号：PCT/US2006045540

申请日：2006-11-28

Applicant: CRYSTAL IS INC ,  BONDOKOV ROBERT T ,  MORGAN KENNETH ,  SLACK GLEN A ,  SCHOWALTER LEO J

Inventor： BONDOKOV ROBERT T ,  MORGAN KENNETH ,  SLACK GLEN A ,  SCHOWALTER LEO J

IPC: C30B23/00 ,  C30B29/40

CPC classification number: C30B23/02 ,  B28D5/00 ,  C23C16/34 ,  C30B23/00 ,  C30B25/02 ,  C30B25/08 ,  C30B25/10 ,  C30B25/18 ,  C30B29/403 ,  C30B33/02 ,  H01L21/0201 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/30625 ,  Y10T428/21

Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities - e.g., a dislocation density below 10 4 cm -3 and an inclusion density below 10 4 cm -3 and/or a MV density below 10 4 cm -3 .

Abstract translation: 降低AlN中的微孔（MV）密度改善了与晶体生长期间的开裂有关的许多问题，抛光期间的蚀刻坑产生，AlN晶片中的光学透明度的降低以及可能的AlN的外延生长期间的生长凹坑形成和/ 或AlGaN。 这有助于实际的晶体生产策略和形成具有低缺陷密度的大的大块AlN晶体 - 例如，位错密度低于10 -4 cm -3，并且包含密度低于 而且，或者低于10 -4 cm -3的MV密度。

公开(公告)号：WO2007062250A2

公开(公告)日：2007-05-31

申请号：PCT/US2006/045540

申请日：2006-11-28

Applicant: CRYSTAL IS, INC. ,  BONDOKOV, Robert, T. ,  MORGAN, Kenneth ,  SLACK, Glen, A. ,  SCHOWALTER, Leo, J.

Inventor： BONDOKOV, Robert, T. ,  MORGAN, Kenneth ,  SLACK, Glen, A. ,  SCHOWALTER, Leo, J.

IPC: C30B23/00 ,  C30B29/40

CPC classification number: C30B33/02 ,  B28D5/00 ,  C23C16/34 ,  C30B23/00 ,  C30B23/02 ,  C30B25/02 ,  C30B25/08 ,  C30B25/10 ,  C30B25/18 ,  C30B29/403 ,  H01L21/0201 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/30625 ,  Y10T428/21

Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities - e.g., a dislocation density below 10 4 cm -3 and an inclusion density below 10 4 cm -3 and/or a MV density below 10 4 cm -3 .

Abstract translation: 减少AlN中的微空隙（MV）密度减少了与晶体生长期间的开裂，抛光期间的蚀刻坑生成，AlN晶片中的光学透明度降低以及可能的生长坑 在AlN和/或AlGaN的外延生长期间形成。 这有利于实际的晶体生产策略和形成具有低缺陷密度的大的块状AlN晶体 - 例如位错密度低于10 4 cm -3和夹杂物密度低于 10 4 cm -3和/或中密度密度低于10 4 cm -3。

公开(公告)号：WO2013021902A1

公开(公告)日：2013-02-14

申请号：PCT/JP2012/069668

申请日：2012-08-02

Applicant: 住友電気工業株式会社 ,  石橋 恵二

Inventor： 石橋　恵二

IPC: H01L21/205 ,  C30B29/36

CPC classification number: H01L21/304 ,  C30B23/025 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/28 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/34 ,  H01L29/36 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  Y10T428/21

Abstract: 　エピタキシャル膜や半導体素子を形成する工程における不良の発生確率を低減することが可能な基板、さらに当該基板を用いた半導体装置および半導体装置の製造方法を提供する。基板（１）は、表面および裏面を有し、当該表面の少なくとも一部分が単結晶炭化珪素からなる基板（１）であって、表面における表面粗さＲａの平均値が０．５ｎｍ以下であって、当該表面粗さＲａの標準偏差σが０．２ｎｍ以下であり、裏面における表面粗さＲａの平均値が０．３ｎｍ以上１０ｎｍ以下であって、当該表面粗さＲａの標準偏差σが３ｎｍ以下であり、表面の直径Ｄが１１０ｍｍ以上である。

Abstract translation: 提供：能够降低用于形成外延膜或半导体元件的工艺中的故障概率的基板; 使用该基板的半导体器件; 以及半导体装置的制造方法。 基板（1）具有前表面和后表面，并且前表面的至少一部分由单晶碳化硅形成。 前表面的表面粗糙度（Ra）平均为0.5nm以下，表面粗糙度（Ra）的标准偏差（s）为0.2nm以下。 背面的表面粗糙度（Ra）平均为0.3nm〜10nm（以下），表面粗糙度（Ra）的标准偏差（s）为3nm以下。 前表面的直径（D）为110mm以上。

公开(公告)号：WO2010083995A3

公开(公告)日：2010-09-23

申请号：PCT/EP2010000328

申请日：2010-01-20

Applicant: FRAUNHOFER GES FORSCHUNG ,  BAGDAHN JOERG ,  BOHNE ALEXANDER ,  SCHOENFELDER STEPHAN ,  FISCHER CAROLA

Inventor： BAGDAHN JOERG ,  BOHNE ALEXANDER ,  SCHOENFELDER STEPHAN ,  FISCHER CAROLA

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/324 ,  H01L31/18

CPC classification number: H01L21/302 ,  H01L21/0201 ,  H01L21/324 ,  H01L31/18

Abstract: The present invention relates to a method of enhancing the strength of a semiconductor wafer or semiconductor chip, the semiconductor wafers being sliced from an ingot or cut from a foil and preprocessed in one or several preprocessing steps prior to further processing steps for generating semiconductor elements. In the proposed method at least one annealing step is performed in addition to the one or several preprocessing steps and processing steps. With the proposed method the fracture strength of semiconductor wafers can be significantly enhanced thus allowing the use of semiconductor wafers with a higher degree of damages and increasing the yield of the whole wafer processing.

Abstract translation: 本发明涉及一种提高半导体晶片或半导体芯片的强度的方法，半导体晶片从锭切割或从箔切割，并且在进一步处理用于产生半导体元件的步骤之前的一个或多个预处理步骤中进行预处理。 在所提出的方法中，除了一个或多个预处理步骤和处理步骤之外还执行至少一个退火步骤。 利用所提出的方法，可以显着提高半导体晶片的断裂强度，从而允许使用具有较高损伤程度的半导体晶片并提高整个晶片处理的产量。

公开(公告)号：WO1984003176A1

公开(公告)日：1984-08-16

申请号：PCT/US1983001989

申请日：1983-12-16

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  LITTLE, Michael, J. ,  BROWN, Roger, H. ,  EFRON, Uzi ,  HOBERG, Clarence, P.

IPC: H01L31/02

CPC classification number: H01L21/0201 ,  G01B11/26 ,  H01L31/0203

Abstract: A semiconductive substrate (1), such as a silicon wafer, is mounted on a baseplate (3), for inclusion in an optical device such as a liquid crystal light valve. An optical flat (9) presses the top surface of the silicon wafer toward the baseplate and against a ring seal (5) surrounding a fluid adhesive (7). The fluid adhesive hydrostatically distributes the force of compression to guarantee optical flatness and self-compensation for the amount fluid adhesive surrounded by the O-ring. The optical flatness of the semiconductor substrate is limited only by the flatness of the optical flat against which it is compressed. Parallel alignment of the optical flat (9), the substrate (1) and the baseplate (3) is achieved by reflecting a laser beam (20) through the semiconductive substrate and observing the interference fringes therein, while adjusting the relative alignment so as to maximize the distance between fringes.

Abstract translation: 诸如硅晶片的半导体基板安装在基板上以包含在诸如液晶光阀的光学装置中。 光学平面将硅晶片的顶表面压向底板并且抵靠围绕流体粘合剂的O形圈密封件。 流体粘合剂可以流体分配压缩力，以保证由O形环包围的流体粘合剂的光学平面度和自我补偿。 半导体衬底的光学平面度仅受到被压缩的光学平面的平坦度的限制。 通过将激光束反射通过半导体基片并观察其中的干涉条纹，同时调整相对对准以使条纹之间的距离最大化，来实现光学平面，基底和基板的平行对准。

公开(公告)号：EP2900850B1

公开(公告)日：2018-11-14

申请号：EP13712085.3

申请日：2013-03-13

Applicant: SixPoint Materials, Inc. ,  Seoul Semiconductor Co., Ltd.

Inventor： HASHIMOTO, Tadao

IPC: H01L21/02 ,  H01L21/66 ,  G01N23/201

CPC classification number: G01N23/207 ,  B24B37/044 ,  C01B21/0632 ,  C01P2002/74 ,  C30B7/105 ,  C30B29/403 ,  C30B29/406 ,  C30B33/00 ,  C30B33/06 ,  H01L21/0201 ,  H01L21/30625 ,  H01L21/78 ,  H01L22/12 ,  H01L29/045 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides, in one instance, a group III nitride wafer sliced from a group III nitride ingot, polished to remove the surface damage layer and tested with x-ray diffraction. The x-ray incident beam is irradiated at an angle less than 15 degree and diffraction peak intensity is evaluated. The group III nitride wafer passing this test has sufficient surface quality for device fabrication. The invention also provides, in one instance, a method of producing group III nitride wafer by slicing a group III nitride ingot, polishing at least one surface of the wafer, and testing the surface quality with x-ray diffraction having an incident beam angle less than 15 degree to the surface. The invention also provides, in an instance, a test method for testing the surface quality of group III nitride wafers using x-ray diffraction having an incident beam angle less than 15 degree to the surface.

公开(公告)号：EP2545582A2

公开(公告)日：2013-01-16

申请号：EP11754183.9

申请日：2011-03-11

Applicant: Sinmat, Inc. ,  University of Florida Research Foundation, Inc.

Inventor： SINGH, Rajiv, K. ,  ARJUNAN, Arul, Chakkaravarthi ,  SINGH, Deepika

IPC: H01L21/20

CPC classification number: H01L21/0201 ,  C30B25/186 ,  C30B29/36 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/30625 ,  H01L29/1608 ,  H01L29/2003

Abstract: An epitaxial article (100) includes an epitaxial substrate (120) providing a substrate surface (103) having a substrate surface composition including crystalline defect or amorphous regions (111) and crystalline non-defect regions (112). The crystalline defect or amorphous regions are recessed from the substrate surface by surface recess regions, where a capping material (108) fills the surface recess regions to provide capped defects 113(a) that extend from a top of the defect regions to the substrate surface. The capping material is compositionally different from the substrate surface composition. An epitaxial layer (115) over the substrate surface provides an average crystalline defect density in at least one area having a size ≥ 0.5 μm
2 that is ≥ two times lower than an average crystalline defect density in that area at or below the substrate surface.