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公开(公告)号：US20240196518A1
公开(公告)日：2024-06-13
申请号：US18583199
申请日：2024-02-21
Applicant: Ampheno Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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公开(公告)号：US11950356B2
公开(公告)日：2024-04-02
申请号：US18079956
申请日：2022-12-13
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, Jr. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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公开(公告)号：US20180324941A1
公开(公告)日：2018-11-08
申请号：US16032284
申请日：2018-07-11
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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公开(公告)号：US20180242467A1
公开(公告)日：2018-08-23
申请号：US15436061
申请日：2017-02-17
Applicant: International Business Machines Corporation
Inventor： Michael J. Shapiro , Brian C. Twichell , Brent W. Yardley
CPC classification number: H05K5/0217 , H05K1/11 , H05K1/181 , H05K7/20727 , H05K2201/07 , H05K2201/10371 , H05K2201/2018 , H05K2201/2027
Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.
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公开(公告)号：US10004154B1
公开(公告)日：2018-06-19
申请号：US15722030
申请日：2017-10-02
Applicant: International Business Machines Corporation
Inventor： Michael J. Shapiro , Brian C. Twichell , Brent W. Yardley
CPC classification number: H05K5/0217 , H05K1/11 , H05K1/181 , H05K7/20727 , H05K2201/07 , H05K2201/10371 , H05K2201/2018 , H05K2201/2027 , Y02P70/611
Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.
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Patent Agency Ranking
公开(公告)号：US20180049312A1
公开(公告)日：2018-02-15
申请号：US15792953
申请日：2017-10-25
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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公开(公告)号：US20180006405A1
公开(公告)日：2018-01-04
申请号：US15598584
申请日：2017-05-18
Applicant: CommScope Technologies LLC
Inventor： Steven Richard Bopp , Neil Ktul Nay
IPC: H01R13/6466 , H01R13/6469 , H01R13/6461 , H05K1/11 , H05K1/02 , H01R24/64 , H01R107/00
CPC classification number: H01R13/6466 , H01R13/6461 , H01R13/6469 , H01R24/64 , H01R2107/00 , H05K1/0228 , H05K1/0239 , H05K1/11 , H05K2201/07 , H05K2201/10189
Abstract: An electrical connector that includes a circuit board having a board substrate that has opposite board surfaces and a thickness measured along an orientation axis that extends between the opposite board surfaces. The circuit board has associated pairs of input and output terminals and signal traces that electrically connect the associated pairs of input and output terminals. The input and output terminals being configured to communicatively coupled to mating and cable conductors, respectively. Each associated pair of input and output terminals is electrically connected through a corresponding signal trace that has a conductive path extending along the board substrate between the corresponding input and output terminals. At least two signal traces form a broadside-coupling region in which the conductive paths of the at least two signal traces are stacked along the orientation axis and spaced apart through the thickness and extend parallel to each other for a crosstalk-reducing distance.
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公开(公告)号：US09807869B2
公开(公告)日：2017-10-31
申请号：US14947166
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, Jr. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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公开(公告)号：US09699894B2
公开(公告)日：2017-07-04
申请号：US14895944
申请日：2015-03-11
Applicant: Seoul National University R&DB Foundation
Inventor： Maenghyo Cho , Kyu Jin Cho , Junghyun Ryu , Je Sung Koh , Jong Gu Lee
CPC classification number: H05K1/028 , G01B7/18 , G01B7/20 , G01N27/00 , G01N27/02 , G01R27/00 , G01R27/02 , G01R27/08 , H05K1/02 , H05K3/12 , H05K2201/07
Abstract: Disclosed herein is a deformation sensing flexible substrate using a pattern formed of a conductive material. The deformation sensing flexible substrate, using the pattern formed of the conductive material, includes a flexible substrate; and conductive patterns in which conductors including a conductive material are arranged and formed to be contactable and non-contact to each other based on deformation of the flexible substrate.
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公开(公告)号：US20170181273A1
公开(公告)日：2017-06-22
申请号：US15379778
申请日：2016-12-15
Inventor： Wilhelm Neukam
CPC classification number: H05K1/0275 , H05K1/0284 , H05K1/03 , H05K3/20 , H05K5/0208 , H05K7/1427 , H05K2201/0388 , H05K2201/07 , H05K2201/09154 , H05K2201/09681
Abstract: An assembly includes a carrier and an electrically conductive mesh, wherein the carrier includes a side surface with an edge, the electrically conductive mesh is attached to the side surface and extends over the edge of the side surface, and the edge has a radius at least as big as a minimal bending radius of electric lines of the electrically conductive mesh.
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