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71.发明授权公开(公告)号：US10073474B2
公开(公告)日：2018-09-11
申请号：US15251289
申请日：2016-08-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Patrik Arno , Alexandre Balmefrezol
CPC classification number: G05F1/46
Abstract: A method of controlling a current flowing through a load including the steps of: applying a first transfer function representative of the load to a first voltage to obtain a second voltage; applying the second voltage to a first terminal of a circuit for generating the current; sampling a third voltage between first and second terminals of the load; comparing the third voltage with the second voltage; and determining the current to be supplied to the load according to the result of the comparison.
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72.发明授权公开(公告)号：US10067550B2
公开(公告)日：2018-09-04
申请号：US15253012
申请日：2016-08-31
Applicant: STMicroelectronics (Alps) SAS
Inventor： Fabien Journet
Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.
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公开(公告)号：US20180130492A1
公开(公告)日：2018-05-10
申请号：US15867223
申请日：2018-01-10
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G11B20/10222 , G06F3/165 , H04B15/04 , H04B2215/065 , H04L7/04
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
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74.发明申请公开(公告)号：US20180063638A1
公开(公告)日：2018-03-01
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
CPC classification number: H04R3/005 , G10K11/346 , H04R1/406 , H04R3/04 , H04R19/005 , H04R2201/003 , H04R2430/23
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
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公开(公告)号：US20180035069A1
公开(公告)日：2018-02-01
申请号：US15725476
申请日：2017-10-05
Applicant: STMicroelectronics (Alps) SAS
Inventor： Serge Hembert
CPC classification number: H04N5/44 , G09G5/006 , G09G2340/02 , G09G2370/20 , G09G2370/22 , H04R2420/05
Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.
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Patent Agency Ranking
公开(公告)号：US20180024584A1
公开(公告)日：2018-01-25
申请号：US15722404
申请日：2017-10-02
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno Lenz
Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.
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公开(公告)号：US09754853B2
公开(公告)日：2017-09-05
申请号：US15050216
申请日：2016-02-22
Inventor： David Auchere , Laurent Marechal , Laurent Schwarz , Yvon Imbs
IPC: H01L23/48 , H01L23/31 , H01L23/64 , H01L23/66 , H01L23/00 , H01Q1/22 , H01L21/48 , H01L21/52 , H01L21/56 , H01L23/13 , H01L23/498
CPC classification number: H01Q1/38 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L21/52 , H01L21/56 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/481 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L24/81 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01L2924/1815 , H01Q1/2283
Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.
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公开(公告)号：US09698565B1
公开(公告)日：2017-07-04
申请号：US15083921
申请日：2016-03-29
Applicant: STMicroelectronics (Alps) SAS
Inventor： Patrik Arno
CPC classification number: H01S5/042 , H01S5/0261 , H01S5/06223 , H01S5/06808 , H01S5/06812 , H05B33/0815
Abstract: A diode control device include a first terminal for receiving a first power supply voltage and a second terminal for receiving a second power supply voltage. A circuit of the diode control device applies a regulated voltage on the anode of the diode in response to a control voltage. The control voltage is equal to a preset voltage when a reference voltage is less than or equal to zero. Conversely, when the reference voltage is greater than zero, the control voltage is equal to the sum of the present voltage and a difference between cathode voltage of the diode and the reference voltage.
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79.发明申请公开(公告)号：US20170062298A1
公开(公告)日：2017-03-02
申请号：US15050216
申请日：2016-02-22
Inventor： David Auchere , Laurent Marechal , Laurent Schwarz , Yvon Imbs
CPC classification number: H01Q1/38 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L21/52 , H01L21/56 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/481 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L24/81 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01L2924/1815 , H01Q1/2283
Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.
Abstract translation: 电子设备包括具有安装面的支撑板和安装在安装面上的集成电路芯片。 封装块嵌入集成电路芯片，封装块在集成电路芯片上方延伸，并围绕集成电路芯片在支撑板的安装面上。 封装块包括具有穿过封装块的孔的前表面以露出至少一部分电触点。 由导电材料制成的层填充孔以与电接触电连接并且进一步在封装块的前表面上延伸。
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公开(公告)号：US20170038788A1
公开(公告)日：2017-02-09
申请号：US15019619
申请日：2016-02-09
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno Lenz
IPC: G05F3/26
Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.
Abstract translation: 一种电压源，其中至少一个第一开关将电压源的第一节点耦合到施加电源电压的至少一个电位的节点，并且至少一个第一电容性元件将第一节点或第二节点 电压源到第一开关的控制节点。
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