公开(公告)号：KR1020050015856A

公开(公告)日：2005-02-21

申请号：KR1020030055029

申请日：2003-08-08

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: H04B1/40

CPC classification number: G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H04L5/1423 ,  H04L25/0272

Abstract: PURPOSE: An SBD(Simultaneous Bi-Directional) transceiver is provided to reduce a size of an output buffer in order to decrease a parasite capacitance, thereby carrying out a stable operation in a frequency. CONSTITUTION: The first differential amplifier(310) consists of the first input end pairs, the first output end pairs, and the first constant current source(321). The second differential amplifier(330) consists of the second input end pairs, the second output end pairs, and the second constant current source(341). The third differential amplifier(350B) consists of the third input end pairs, the third output end pairs, and the third constant current source(363). The fourth differential amplifier(350A) consists of the fourth input end pairs, the fourth output end pairs, and the fourth constant current source(373). Each of the first input end pairs is connected to each of the second input end pairs, while each of the first output end pairs is connected to each of the fourth input end pairs. Each of the second output end pairs is connected to each of the third input end pairs, while each of the third output end pairs is connected to each of the fourth output end pairs.

Abstract translation: 目的：提供SBD（同时双向）收发器以减小输出缓冲器的尺寸，以减少寄生电容，从而在频率下进行稳定的操作。 构成：第一差分放大器（310）由第一输入端对，第一输出端对和第一恒流源（321）组成。 第二差分放大器（330）由第二输入端对，第二输出端对和第二恒流源（341）组成。 第三差分放大器（350B）由第三输入端对，第三输出端对和第三恒流源（363）组成。 第四差分放大器（350A）由第四输入端对，第四输出端对和第四恒流源（373）组成。 每个第一输入端对连接到每个第二输入端对，而第一输出端对中的每一个连接到每个第四输入端对。 第二输出端对中的每一个连接到每个第三输入端对，而第三输出端对中的每一个连接到第四输出端对中的每一个。

公开(公告)号：KR1020040086037A

公开(公告)日：2004-10-08

申请号：KR1020030027797

申请日：2003-04-30

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: G06F13/00

Abstract: PURPOSE: A digital picturing device and a data transfer mode selecting method thereof are provided to perform data communication with a PC more smoothly by previously selecting one of the mode to transfer the data of a currently pictured image to the PC in real-time or the mode to transfer the previously stored image data to the PC. CONSTITUTION: A main storage(220) stores each firmware for two data transfer modes transferring the image data pictured through a camera(210) to an external device(100) in different methods and each descriptor including the ID information of the firmware. A mode selector(254) outputs a mode selection signal for one of the transfer modes. A transmitting module(280) transfers the image data to the external device in the different methods for each transfer mode. A controller(290) controls the transmitting module by setting the transfer method matched with the selected transfer mode, reads the descriptor of the firmware matched with the transfer mode from the main storage if the transmitting module is connected to the external device, and provides the read descriptor to the transmitting module.

Abstract translation: 目的：提供一种数字图像设备及其数据传输模式选择方法，通过预先选择将当前图像数据的数据实时传输到PC的模式，或者 模式将以前存储的图像数据传送到PC。 构成：主存储器（220）存储用于通过不同方法将图像数据通过摄像机（210）传送到外部设备（100）的两种数据传输模式，每个描述符包括固件的ID信息。 模式选择器（254）输出用于传送模式之一的模式选择信号。 发送模块（280）以每种传输模式的不同方法将图像数据传送到外部设备。 控制器（290）通过设置与选择的传送模式相匹配的传送方法来控制发送模块，如果发送模块连接到外部设备，则从主存储器读取与传送模式匹配的固件的描述符，并且提供 读描述符到发送模块。

公开(公告)号：KR1020040049542A

公开(公告)日：2004-06-12

申请号：KR1020020077348

申请日：2002-12-06

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: H01L21/66

CPC classification number: G01R31/31926

Abstract: PURPOSE: A semiconductor device is provided to simultaneously transmit data in both directions and perform a test process on both directions by using conventional ATE(automatic test equipment). CONSTITUTION: At least two pads are included in the first port. At least two pads are included in the second port. A normal data path connects at least one pad of the two pads of the first port with an inner circuit of the semiconductor device. A transmission path is connected between at least one pad of the two pads of the first port and at least one pad of the two pads of the second port. A test path is connected between at least one pad of the two pads of the first port and at least one pad of the two pads of the second port. A selection circuit selects the transmission path or the test path.

Abstract translation: 目的：提供半导体器件，通过使用传统的ATE（自动测试设备）在两个方向上同时传输数据并执行两个方向的测试过程。 构成：第一个端口至少包含两个焊盘。 在第二个端口中至少包含两个焊盘。 正常数据路径将第一端口的两个焊盘的至少一个焊盘与半导体器件的内部电路连接。 传输路径连接在第一端口的两个焊盘的至少一个焊盘和第二端口的两个焊盘的至少一个焊盘之间。 测试路径连接在第一端口的两个焊盘的至少一个焊盘和第二端口的两个焊盘的至少一个焊盘之间。 选择电路选择传输路径或测试路径。

公开(公告)号：KR1020040028702A

公开(公告)日：2004-04-03

申请号：KR1020037008605

申请日：2002-06-24

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: G06F12/00

Abstract: PURPOSE: A memory module equipped with a path transferring high speed data and low speed data, and a memory system equipped with the same are provided to design various shape of memory modules by increasing degree of freedom as decreasing a pin number connected to a mother board, and to transfer data at high speed by decreasing crosstalk and loss or attenuation of the transferred data. CONSTITUTION: A plurality of memories(55_1-55_9) is installed to the memory module(50). The first connector(57) installed to a position of the memory module receives the low speed data. The second connectors(51_1-51_9) installed to the position different from the first connector transfer the high speed data and connect to a transfer line(33) or an optical fiber. Converting circuits(53_1-53_9) receive/convert the data inputted through the second connector into parallel data and output a result to the memories. Otherwise, the converting circuits receive/convert the data output from the memories into serial data and output the result to the second connector.

Abstract translation: 目的：提供一种配备有传输高速数据和低速数据的路径的存储器模块以及配备该存储器模块的存储器系统，以通过增加自由度来设计各种形状的存储器模块，从而降低连接到母板的引脚数 ，并通过减少传输数据的串扰和丢失或衰减来高速传输数据。 构成：将多个存储器（55_1-55_9）安装到存储器模块（50）。 安装到存储模块的位置的第一连接器（57）接收低速数据。 安装到与第一连接器不同的位置的第二连接器（51_1-51_9）传送高速数据并连接到传输线（33）或光纤。 转换电路（53_1-53_9）将通过第二连接器输入的数据接收/转换为并行数据并将结果输出到存储器。 否则，转换电路将从存储器输出的数据接收/转换为串行数据，并将结果输出到第二连接器。

公开(公告)号：KR100374630B1

公开(公告)日：2003-03-03

申请号：KR1019990059440

申请日：1999-12-20

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: H05K13/08

CPC classification number: G01R1/0433

Abstract: A socket and a printed circuit board for testing a semiconductor device packaged by a chip scaled package (CSP) method, and a semiconductor device testing method are provided. In order to test the semiconductor device packaged by a CSP method, the upper wall of the testing socket has a socket aperture formed to expose the pads of the semiconductor device to be tested to the outside of the testing socket. The testing socket may be mounted under the printed circuit board. The printed circuit board has a board aperture formed over the socket aperture. The pads of a semiconductor device are directly probed through both the socket aperture and the board aperture, so that the waveforms of a semiconductor device can be measured.

Abstract translation: 提供了用于测试通过芯片缩放封装（CSP）方法封装的半导体器件的插座和印刷电路板以及半导体器件测试方法。 为了测试通过CSP方法封装的半导体器件，测试插座的上壁具有形成的插孔，以将待测试的半导体器件的焊盘暴露于测试插座的外部。 测试插座可以安装在印刷电路板下面。 印刷电路板具有形成在插座孔上方的板孔。 半导体器件的焊盘直接通过插座孔和板孔两者进行探测，从而可以测量半导体器件的波形。

公开(公告)号：KR1020020095357A

公开(公告)日：2002-12-26

申请号：KR1020010033551

申请日：2001-06-14

Applicant: 삼성전자주식회사

Inventor： 김경호 ,  최정환 ,  허락원

IPC: G06F13/00

CPC classification number: G11C11/409 ,  G11C7/1048 ,  G11C11/4076

Abstract: PURPOSE: An information processing system is provided to make the flight time of a clock signal identical to that of a data signal so that it can stably operate a Rambus DRAM mounted in a memory module though an operation frequency gets higher. CONSTITUTION: The system comprises a memory controller(110), and the first and second RIMM(Rambus in-line memory module, 120, 130). The memory controller(110) and the first and second RIMM(120, 130) are connected to a data bus(140), a clock line(150) and a reference voltage line(160). The clock line(150) has a closed loop structure comprising the first clock line segment(151) and the second clock line segment(152). Each clock line segments(151, 152) include a U-turn portion, the first terminal and the second terminal. The first terminals of both the clock line segments(151, 152) are commonly connected to a clock generator(170). The second terminals of both the clock line segments(151, 152) are connected to a terminal voltage via a terminal resistor. Accordingly, the distance between the clock generator(170) and the terminal resistor is identical to a length of the data bus(140), and each length of the clock line segments(151, 152) is also identical to a length of the data bus(140). As a result, the flight time of the clock signal gets identical to that of the data signal.

Abstract translation: 目的：提供一种信息处理系统，使时钟信号的飞行时间与数据信号的时间信号相同，使得它可以稳定地操作安装在存储器模块中的Rambus DRAM，尽管操作频率变高。 构成：系统包括存储器控制器（110）和第一和第二RIMM（Rambus在线存储器模块，120,130）。 存储器控制器（110）和第一和第二RIMM（120,130）连接到数据总线（140），时钟线（150）和参考电压线（160）。 时钟线（150）具有包括第一时钟线段（151）和第二时钟线段（152）的闭环结构。 每个时钟线段（151,152）包括U形转弯部分，第一端子和第二端子。 两个时钟线段（151,152）的第一个端子共同连接到一个时钟发生器（170）。 时钟线段（151,152）的第二端子通过端子电阻器连接到端子电压。 因此，时钟发生器（170）和端子电阻器之间的距离与数据总线（140）的长度相同，并且时钟线段（151,152）的每个长度也与数据的长度相同 总线（140）。 结果，时钟信号的飞行时间与数据信号的飞行时间相同。

公开(公告)号：KR1020010057242A

公开(公告)日：2001-07-04

申请号：KR1019990059440

申请日：1999-12-20

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: H05K13/08

CPC classification number: G01R1/0433

Abstract: PURPOSE: A semiconductor device socket, printed circuit board and testing method for semiconductor device is provided to directly detect waveform at the semiconductor surface during high speed operation of semiconductor device which is packaged a chip scaled package system. CONSTITUTION: A socket(60) for testing a semiconductor device which is packaged by a chip scaled package system, comprises outer walls(61), an upper wall and a lower support for fixing the semiconductor device; a plurality of ball contact springs(62) contacting each of balls connected to pads of the semiconductor device, and which penetrate through the upper wall; and an opening(68) formed at the upper wall of the test socket so as to allow pads of the semiconductor device to be exposed outward from the test socket. A printed circuit board includes a bottom surface to which the upper wall of the socket is attached, and an opening formed to allow the opening formed at the socket to be opened.

Abstract translation: 目的：提供一种用于半导体器件的半导体器件插座，印刷电路板和测试方法，用于在半导体器件的高速运行期间直接检测在半导体表面处的波形，该半导体器件封装有芯片定标的封装系统。 构成：用于测试由芯片尺寸封装系统封装的半导体器件的插座（60），包括用于固定半导体器件的外壁（61），上壁和下支撑件; 多个球接触弹簧（62），其接触连接到所述半导体器件的焊盘并穿过所述上壁的每个滚珠; 以及形成在测试插座的上壁处的开口（68），以便允许半导体器件的焊盘从测试插座向外露出。 印刷电路板包括安装有插座的上壁的底面和形成为允许形成在插座上的开口的开口的开口。

公开(公告)号：KR100281898B1

公开(公告)日：2001-02-15

申请号：KR1019980029291

申请日：1998-07-21

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: G11C29/00

Abstract: 데이터의 듀티 사이클(duty cycle)을 보정하는 듀티 사이클 보정 회로 및 그 방법이 개시된다. 클럭 듀티 사이클 보정기는 클럭 신호를 입력하고 상기 클럭 신호의 듀티 사이클 에러에 각각 비례하되 그 비율이 다른 제1 및 제2 듀티 사이클 제어 신호와 상기 클럭 신호의 듀티 사이클이 보정된 내부 클럭 신호를 발생한다. 제1 기준 전압 발생기는 제1 기준 전압을 발생한다. 제2 기준 전압 발생기는 상기 제1 기준 전압과 상기 제1 및 제2 듀티 사이클 제어 신호들을 입력하고 상기 제1 기준 전압과 상기 제1 및 제2 듀티 사이클 제어 신호들을 합산 및 증폭하여 제2 기준 전압을 발생한다. 데이터 수신기는 데이터와 상기 제2 기준 전압 및 상기 내부 클럭 신호를 입력하고 상기 내부 클럭 신호에 동기되어 상기 데이터와 상기 제2 기준 전압을 비교 및 증폭하여 상기 데이터의 듀티 사이클을 보정한다. 따라서, 입력되는 데이터의 불완전한 듀티 사이클이 50%로 보정된다.

公开(公告)号：KR1020000019706A

公开(公告)日：2000-04-15

申请号：KR1019980037945

申请日：1998-09-15

Applicant: 삼성전자주식회사

Inventor： 최정환 ,  박찬종

IPC: H01L23/36

Abstract: PURPOSE: A semiconductor device module and its radiation system is provided which have new construction, operate more stably by improving the heat radiation problem to prevent bad operation due to temperature rise caused by tendency of the semiconductor device towards high-speed and high-capacity. CONSTITUTION: A semiconductor device module(10) comprises many semiconductor devices,printed circuit board on which the semiconductor devices are mounted and which are combined by circuit pattern to accomplish electrical connection, and a heat radiation plate(16) which is mounted to the printed circuit board to radiate outward the heat occurred in response to the operation of the semiconductor device. A thermoelectric cooler(17) operated according to the operation of the semiconductor device is arranged on the heat radiation plate. A heat radiation system(20) comprises the semiconductor devices, the printed circuit board, the heat radiation plate, a semiconductor device module having thermoelectric cooler mounted to the heat radiation plate, a temperature sensor(22) for measuring temperature of the semiconductor device module, and a controller(21) for driving the thermoelectric cooler when temperature value measured by the sensor is above a predetermined temperature. Accordingly, overall temperature of the module is rapidly lowered since heat is rapidly dissipated and radiated. Also, since volume of the cooler is small, overall volume occupied by the module is not large. The resultant system has low noise because there is no great noise source like cooling fan.

Abstract translation: 目的：提供一种半导体器件模块及其辐射系统，其具有新的结构，通过改善散热问题更稳定地工作，以防止由于半导体器件朝向高速和大容量的趋势而引起的温度上升导致的不良操作。 构成：半导体器件模块（10）包括许多半导体器件，其上安装有半导体器件的印刷电路板，并且通过电路图案组合以实现电连接;以及散热板（16），其安装到印刷 电路板向外辐射发生的响应于半导体器件的操作的热量。 根据半导体器件的操作操作的热电冷却器（17）布置在散热板上。 散热系统（20）包括半导体器件，印刷电路板，散热板，具有安装在散热板上的热电冷却器的半导体器件模块，用于测量半导体器件模块的温度的温度传感器（22） 以及用于当所述传感器测量的温度值高于预定温度时驱动所述热电冷却器的控制器（21）。 因此，由于热被快速消散和辐射，所以模块的总体温度迅速降低。 此外，由于冷却器的体积小，所以模块占用的总体积不大。 所产生的系统噪音低，因为没有像冷却风扇那样的噪音源。

公开(公告)号：KR1020000015328A

公开(公告)日：2000-03-15

申请号：KR1019980035177

申请日：1998-08-28

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: H01L23/28

Abstract: PURPOSE: A substrate for mounting a ball grid array package is provided, which easily mounts and separates a memory device of a ball grid array package to a substrate. CONSTITUTION: The substrate for mounting a ball grid array package comprises: a substrate body (12) having an upper surface and a lower surface; a wire pattern (18) to be formed at one surface of the substrate body (12) for connecting a BGA package (30) to an external electronic device; and a clip (20) to be arranged at both sides of the substrate body (12) for fixing the BGA package (30) to be mounted on the substrate body (12), including a rotation bar (26) to be arranged at a distance position of the substrate body (12) for performing a rotation movement, a supporting bar (28) to be connected to both terminals of the rotation bar (26) for guiding the rotation movement, and a fixing bar (24) to be formed with the rotation bar (26) in one body. Thereby, it is possible to increase the memory capacity.

Abstract translation: 目的：提供用于安装球栅阵列封装的基板，其容易地将球栅阵列封装的存储器件安装并分离到基板。 构成：用于安装球栅阵列封装的基板包括：具有上表面和下表面的基板主体（12）; 形成在用于将BGA封装（30）连接到外部电子装置的基板主体（12）的一个表面处的线图案（18） 和布置在基板主体（12）的两侧的夹子（20），用于固定待安装在基板主体（12）上的BGA封装（30），包括一个旋转杆（26） 用于进行旋转运动的基板主体（12）的距离位置，连接到用于引导旋转运动的旋转杆（26）的两个端子的支撑杆（28）和待形成的固定杆（24） 旋转杆（26）在一体内。 由此，能够提高存储容量。