公开(公告)号：KR1020040096789A

公开(公告)日：2004-11-17

申请号：KR1020040032765

申请日：2004-05-10

Applicant: 한국과학기술원

Inventor： 유회준

IPC: B25J7/00

Abstract: PURPOSE: An SoC(System On a Chip) robot system and an operating method thereof are provided to implement an improved game robot by providing various platforms to a robot brain and connecting the brain to a microcontroller, an image processing unit, and a communicating unit. CONSTITUTION: An SoC robot system is composed of a brain unit(10), an image sensor unit(20), and a robot body(30). The brain unit receives image data from the image sensor unit, and transmits a driving command to the robot body. The robot body operates by the command received from the brain unit, and includes a microprocessor, a wire module communicating with the brain unit, a driving unit for controlling motion, and a firing control unit. The brain unit includes an SoC platform, a CPU-IP for processing a command, a memory-IP for storing data, a communication-IP, an image sensor interface-IP for processing image data, an FPGA interface-IP processing image data and communicating with the CPU-IP, an GPIO-IP for providing input/output channels, and a ROM for storing a control program. The image sensor unit includes a camera, a plurality of registers for operating functions set in advance, an image debugging unit for debugging image data, and a monitor.

Abstract translation: 目的：提供一种SoC（片上系统）机器人系统及其操作方法，以通过向机器人脑提供各种平台并将大脑连接到微控制器，图像处理单元和通信单元来实现改进的游戏机器人 。 构成：SoC机器人系统由脑单元（10），图像传感器单元（20）和机器人主体（30）组成。 大脑单元从图像传感器单元接收图像数据，并向机器人主体发送驾驶命令。 机器人主体通过从大脑单元接收到的命令进行操作，并且包括微处理器，与大脑单元通信的线模块，用于控制运动的驱动单元和点火控制单元。 大脑单元包括一个SoC平台，用于处理命令的CPU-IP，用于存储数据的存储器IP，通信IP，用于处理图像数据的图像传感器接口-IP，FPGA接口-IP处理图像数据和 与CPU-IP通信，用于提供输入/输出通道的GPIO-IP以及用于存储控制程序的ROM。 图像传感器单元包括摄像机，用于预先设置的操作功能的多个寄存器，用于调试图像数据的图像调试单元和监视器。

公开(公告)号：KR100444911B1

公开(公告)日：2004-08-21

申请号：KR1020020005138

申请日：2002-01-29

Applicant: 한국과학기술원

Inventor： 이재서 ,  유회준

IPC: H03F3/45

Abstract: PURPOSE: A differential trans impedance amplifier for a photo diode is provided, which reduce an area of a preamplifier and has a high speed, a high gain, a low noise and wide band characteristics. CONSTITUTION: The first buffer(10) of control cascode structure insulates a photo diode by receiving an output of the photo diode converting an optical pulse signal into a photovoltaic force. The second buffer(20) is formed symmetrically to the first buffer for symmetry of a differential structure. A differential amplifier(30) receives the outputs of the first buffer and the second buffer. A threshold voltage compensation load stage(40) is intervened between the differential amplifier and a power supply to widen a dynamic range with a wide swing width. The third buffer(50) of cascode structure obtains DC level shifting and low power consumption by receiving a differential output value of the differential amplifier. And an output stage(60) enables a high speed operation by widening a bandwidth of a device with a shunt peaking technology as to the output of the third buffer.

Abstract translation: 目的：提供一个用于光电二极管的差分传输阻抗放大器，它可以减小前置放大器的面积，并具有高速，高增益，低噪声和宽带特性。 构成：控制共源共栅结构的第一缓冲器（10）通过接收光电二极管的输出将光脉冲信号转换成光电力而使光电二极管绝缘。 第二缓冲器（20）相对于第一缓冲器对称地形成，用于差分结构的对称性。 差分放大器（30）接收第一缓冲器和第二缓冲器的输出。 阈值电压补偿负载级（40）被插入在差分放大器和电源之间以扩大具有宽摆幅的动态范围。 通过接收差分放大器的差分输出值，共源共栅结构的第三缓冲器（50）获得DC电平移位和低功耗。 并且输出级（60）通过使用并联峰化技术扩大装置的带宽来实现高速操作，以关于第三缓冲器的输出。

公开(公告)号：KR1020030074856A

公开(公告)日：2003-09-22

申请号：KR1020020013838

申请日：2002-03-14

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F13/38

Abstract: PURPOSE: A device for controlling a buffer memory of a computer system is provided to implement a buffer system of a low-power effectively and use an internal memory as a scratch pad memory by partially activating a bank of an internal buffer memory according to a flow of the current data and the number of entry numbers of a queue and applying an adaptability in a queue system for connecting two components which create and consume data. CONSTITUTION: An output latch(40) is operated as a virtual queue when data stored in a buffer memory(20) are transmitted to a consumption component(30) or the buffer memory(20) is used as a scratch pad memory. A buffer controller(50) controls data of the buffer memory(20), and delays an operation of a processor(10) or the component(30) when an overflow or underflow of the buffer memory(20) is generated. The buffer controller(50) decides an active point(Act_point) according to the number of internal entry numbers of the buffer memory(20) and the number of necessary bank numbers. The buffer controller(50) separates an output latch(40) for using the buffer memory(20) as the scratch pad memory. A bank controller(60) activates a bank of the buffer memory(20) as a circular form by the active point(Act_point) of the buffer controller(50).

Abstract translation: 目的：提供一种用于控制计算机系统的缓冲存储器的设备，以有效地实现低功率的缓冲系统，并且通过根据流程部分地激活内部缓冲存储器组，并且使用内部存储器作为临时存储器 的当前数据和队列的入口号码，并在队列系统中应用适应性来连接创建和使用数据的两个组件。 构成：当将存储在缓冲存储器（20）中的数据传送到消耗部件（30）或缓冲存储器（20）用作暂存器存储器时，输出锁存器（40）作为虚拟队列操作。 当产生缓冲存储器（20）的上溢或下溢时，缓冲器控制器（50）控制缓冲存储器（20）的数据，并延迟处理器（10）或组件（30）的操作。 缓冲器控制器（50）根据缓冲存储器（20）的内部条目号的数量和所需的存储体号的数量来决定活动点（Act_point）。 缓冲器控制器（50）将用于使用缓冲存储器（20）的输出锁存器（40）分离为临时存储器。 银行控制器（60）通过缓冲控制器（50）的活动点（Act_point）将循环形式的缓冲存储器（20）的一行激活。

公开(公告)号：KR1020020050413A

公开(公告)日：2002-06-27

申请号：KR1020000079561

申请日：2000-12-21

Applicant: 한국과학기술원

Inventor： 박용하 ,  유회준

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  G06F13/4072 ,  H03K19/0013

Abstract: PURPOSE: A low power bus driver using a current feedback is provided, which drives a bus operating in a high speed in an integrated circuit with low power consumption and a minimum area, using a method to restrict an operation voltage of a bus driving signal. CONSTITUTION: The low power bus driver includes a transmitter part(10) and a receiver part(20), and the transmitter part includes a pre-driver(100) and a main driver(200). A NAND gate outputs a NAND signal by receiving two logic signals, and a NOR gate outputs a NOR signal by receiving two input signals including one of input signals of the NAND gate. A feedback loop PMOS receives an output signal of the NAND gate through a gate, and its drain is connected to the gate electrically. A feedback loop NMOS receives an output signal of the NOR gate through a gate, and its drain is connected electrically to the gate and its source is connected to a source of the feedback loop PMOS. A VCC is inputted to a source of a PMOS driver and its gate is connected to the drain of the feedback loop PMOS. In a driver NMOS, a gate is connected electrically to the drain of the feedback loop NMOS and a drain is connected electrically to a drain of the driver PMOS and a source is grounded. And an output line is connected to the drain of the driver NMOS and the drain of the driver PMOS and the source of the feedback loop NMOS and the source of the feedback loop PMOS in common, and also is connected to an input port of a bus(30).

Abstract translation: 目的：提供使用电流反馈的低功率总线驱动器，通过使用限制总线驱动信号的工作电压的方法，驱动总线在低功耗和最小面积的集成电路中高速运行。 构成：低功率总线驱动器包括发射器部分（10）和接收器部分（20），发射器部分包括预驱动器（100）和主驱动器（200）。 NAND门通过接收两个逻辑信号输出NAND信号，NOR门通过接收包括NAND门的输入信号之一的两个输入信号来输出NOR信号。 反馈环路PMOS通过栅极接收与非门的输出信号，其漏极电连接到栅极。 反馈环路NMOS通过栅极接收或非门的输出信号，其漏极与栅极电连接，其源极连接到反馈环路PMOS的源极。 VCC被输入到PMOS驱动器的源极，并且其栅极连接到反馈环路PMOS的漏极。 在驱动器NMOS中，栅极电连接到反馈环路NMOS的漏极，漏极与驱动器PMOS的漏极电连接，源极接地。 并且输出线连接到驱动器NMOS的漏极和驱动器PMOS的漏极以及反馈环路NMOS的源极和反馈环路PMOS的源极，并且还连接到总线的输入端口 （30）。

公开(公告)号：KR100326939B1

公开(公告)日：2002-03-13

申请号：KR1019990037216

申请日：1999-09-02

Applicant: 한국과학기술원

Inventor： 유회준 ,  윤치원

IPC: G11C7/00

CPC classification number: G11C11/408 ,  G11C7/1006 ,  G11C7/1039 ,  G11C8/00

Abstract: 전기신호의논리상태를저장가능한복수개의메모리셀 코어가 N개의행과 M개의열로배열되어있는메모리셀 어레이와, 행또는열로배열되어있는각 메모리셀 코어의어드레스와비트라인의인에이블을통해해당셀 코어에저장되어잇는데이터의리딩또는라이팅동작을수행할수 있는메모리구조에관한것으로특히, 메모리셀 어레이의어드레스라인은소정개수씩묶어하나의군으로형성하고각 군을대표하는메인어드레스라인과각 군을형성하는어드레스라인들을해당메인어드레스라인의서브어드레스라인으로형성하고, 특정제어시스템으로부터어드레스데이터를입력받아상기메인어드레스라인을억세스하며억세스되어진메인어드레스라인에속하는서브어드레스라인을선택하는것을특징으로하는열 경로에서의파이프라인구조를갖는메모리를제공하여어드레스디코딩동작과셀코어에서의동작을분리할수 있으며, 어드레스다중화방식을그대로사용하여기존의시스템과호환성을유지할수 있다.

公开(公告)号：KR100302849B1

公开(公告)日：2001-11-05

申请号：KR1019990037215

申请日：1999-09-02

Applicant: 한국과학기술원

Inventor： 유회준 ,  한선호 ,  이주호

IPC: H03K23/42

Abstract: 본발명은동기카운터에관한것으로특히, 특정주기의동기신호를동기신호입력단에동시에입력받는일렬로나열되어있으며, 첫번째트리거에지플립플롭만은자신의반전출력을데이터입력으로하는 N개의 1차트리거에지플립플롭층과, 상기 1차트리거에지플립플롭층의첫 번째트리거에지플립플롭의비반전출력을동기신호입력단에동시에입력받는일렬로나열되어있으며, 첫번째트리거에지플립플롭만은자신의반전출력을데이터입력으로하며모든플립플롭의비반전출력단은자신의배열위치보다후단의배열위치를갖는 1차트리거에지플립플롭층의트리거에지플립플롭의데이터입력단에연결되어있는 N-1개의 2차트리거에지플립플롭층, 및상기 1차및 2차트리거에지플립플롭층간의상관관계에따라상기 2차트리거에지플립플롭층위로 m개의트리거에지플립플롭층이존재하는것을특징으로하는모든카운터의출력이한 단의플립플롭지연시간을갖는동기카운터를제공하여많은카운팅비트의구성과동일한타이밍에카운터의출력을내보내면서도빠른지연시간을갖는카운터를구성하여고속의카운팅이필요한시스템에사용가능하다.

公开(公告)号：KR100293256B1

公开(公告)日：2001-06-15

申请号：KR1019990005928

申请日：1999-02-23

Applicant: 한국과학기술원

Inventor： 유회준 ,  한선호 ,  이주호

IPC: H03L7/00

Abstract: 본발명은빠른클럭동기시간과작은지터(jitter) 특성을갖는클럭동기회로에관한것으로서, 보다상세하게는기존의 DLL(Delay Locked Loop), PLL(Phase Locked Loop)의아날로그회로와 DL(Delay Line)의디지털회로의장점을모두가지도록아날로그 VCDL(Voltage Controlled Delay Line)과디지털 FDL(Fixed Delay Line)로구성된혼합모드클럭동기회로(Mixed Mode DLL)에관한것으로서, 외부클럭과내부클럭을동기시키기위하여초기에내부클럭과외부클럭사이의큰 위상차를 FDL에의하여 2클럭사이클만에작게하여클럭을일단동기시키고, 이후남아있는위상차에대해서는아날로그 VCDL의지연시간을미세하게변화시켜클럭을빠른시간안에완벽하게동기시킬수 있도록구성하여, 기존의방식에비해빠른클럭동기시간과더욱개선된저 지터특성을가지므로저전력이면서고속의클럭인터페이스를필요로하는곳에채용될수 있어고속데이터전송이요구되는칩에유용하게사용될수 있는것이다.

公开(公告)号：KR100291628B1

公开(公告)日：2001-05-15

申请号：KR1019990023092

申请日：1999-06-19

Applicant: 한국과학기술원

Inventor： 박세정 ,  유회준 ,  박규호

IPC: G06T1/60

CPC classification number: G06F12/0862 ,  G06T1/60

Abstract: 본발명은 PC용고성능 3차원그래픽카드, 3차원게임기및 기타소형고성능 3차원그래픽을요구하는분야에적용가능한텍스쳐맵핑용캐쉬메모리에관한것으로서, 특히 3차원그래픽시스템에서트라이리니어인터폴레이션(trilinear interpolation)을이용하는밉맵핑(mipmapping)에의한텍스쳐맵핑가속을위하여, 적당한크기의워킹셋만큼의텍스쳐만을저장하며, 한클럭사이클만에트라이리니어인터폴레이션을수행하기위하여필요한 8개의텍셀을모두엑세스하여최종텍셀의값을구해낼 수있는특수한구조를갖는캐쉬메모리와앞으로필요하게될 텍스쳐들을하드웨어적으로예측하여프리페칭(hardware-predicted prefetching) 하므로써캐쉬미스(cache miss) 시에발생하는페널티(penalty)를줄일수 있는캐쉬미스페널티저감방법에관한것이다. 본발명의캐쉬메모리및 캐쉬미스페널티저감방법은기존의하드웨어적인텍스쳐맵핑가속화방법보다다양한크기의텍스쳐이미지들에대해서효율적으로적용이가능하면서, 소형저가의시스템에서도하드웨어적인텍스쳐맵핑가속을가능하게한다.

公开(公告)号：KR1020000073779A

公开(公告)日：2000-12-05

申请号：KR1019990017281

申请日：1999-05-14

Applicant: 한국과학기술원 ,  신성전자공업 주식회사

Inventor： 신형철 ,  유회준 ,  제민규 ,  한승호

IPC: H03B5/30

CPC classification number: H01L27/0629 ,  H03J2200/10 ,  H03L1/026

Abstract: PURPOSE: A capacitor block for temperature adaptation and a temperature compensated crystal oscillator using thereof are provided to perform the error compensation of the resonance frequency according to the temperature variation efficiently and to solve the non-monotonic while the silicon area is deceased. CONSTITUTION: A temperature compensated crystal oscillator using capacitor block for temperature adaptation comprises a crystal oscillator(60), a temperature sensing circuit(61), an analog-digital converter(62), a controller(63), a memory(64) and a decoder(65). The crystal oscillator(60) outputs the variable resonance frequency according to the temperature and load capacitor. The temperature sensing circuit(61) senses the around temperature of the crystal oscillator(60) and outputs the electrical signal. The analog-digital converter(62) converts the sensed signal to digital type. The controller(63) reads a unit capacitor switch control code by using the present temperature sensed from the analog-digital convertor(62) and the temperature area boundary value stored at the memory(64), controls the unit capacitor and varies the load capacitance of the crystal oscillator(60). The memory(64) stores the unit capacitor switch control code according to the temperature. The decoder(65) provides the switch control code provided from the controller(63) to two capacitor bank(66,67).

Abstract translation: 目的：提供一种用于温度适应的电容器块和使用其的温度补偿晶体振荡器，以有效地根据温度变化执行谐振频率的误差补偿，并且在硅面积下降时解决非单调谐波。 构成：使用电容器块进行温度补偿的温度补偿晶体振荡器包括晶体振荡器（60），温度感测电路（61），模拟数字转换器（62），控制器（63），存储器（64）和 解码器（65）。 晶体振荡器（60）根据温度和负载电容输出可变谐振频率。 温度检测电路（61）感测晶体振荡器（60）的周围温度并输出电信号。 模拟数字转换器（62）将感测到的信号转换为数字类型。 控制器（63）通过使用从模拟数字转换器（62）感测的当前温度和存储在存储器（64）中的温度区域边界值来读取单位电容器开关控制代码，控制单位电容器并改变负载电容 的晶体振荡器（60）。 存储器（64）根据温度存储单位电容器开关控制代码。 解码器（65）将从控制器（63）提供的开关控制代码提供给两个电容器组（66,67）。

公开(公告)号：KR102228639B1

公开(公告)日：2021-03-16

申请号：KR1020190097588

申请日：2019-08-09

Applicant: 한국과학기술원

Inventor： 유회준 ,  한동현

IPC: G06F3/01 ,  G06F3/00 ,  G06K9/00 ,  H04N13/271

Abstract: 본발명은 3차원깊이추출카메라로부터전달된 3차원깊이정보를이용하여손동작을추적하는추적부를포함하는손동작추적장치를이용하여, 손동작을추출하되, 상기 3차원깊이추출카메라로부터전달된, 사용자의손 모양및 손동작에대한 3차원깊이정보에의거하여사용자의손 모양정보를반영한최적의 3차원손 모델을자동으로생성하는손 모델자동생성단계; 및상기 3차원깊이추출카메라를통해촬영된사용자의손동작에대한 3차원깊이정보의입력에응답하여, 상기 3차원깊이정보에포함된잡음을제거하는잡음제거단계를수행한후 상기자동생성된 3차원손 모델을이용하여사용자의손동작을추적하는손동작추적단계를수행한다. 따라서, 본발명은정확하고편리하게손모델을생성할수 있으며, 이로인해손동작을정확하게추적할수 있는장점이있다.