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公开(公告)号：DE19616412B4
公开(公告)日：2008-04-03
申请号：DE19616412
申请日：1996-04-24
Applicant: DENSO CORP
Inventor： NONOYAMA SHIGERU , WATANABE TAKAMOTO
Abstract: A physical amount detecting apparatus, preferably, an acceleration sensor, includes a sensor element, an A/D converter, a control unit and an activation unit. The sensor element is activated by a supply voltage and outputs an electric signal in accordance with a predetermined physical amount. The A/D converter digitizes an analog electric signal and outputs digital data. The control unit calculates a control amount in order to control the sensor element, as the electric signal is set to a predetermined output, based on the digital data, and generates a control signal in accordance with the control amount. The activation unit activates the sensor element in accordance with the control signal. As a result, the control unit outputs a detecting signal indicating a physical amount in accordance with the control amount or the control signal.
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公开(公告)号：DE102006056411A1
公开(公告)日：2007-06-14
申请号：DE102006056411
申请日：2006-11-29
Applicant: DENSO CORP
Inventor： WATANABE TAKAMOTO
IPC: H03M1/50 , H03K5/04 , H03K5/13 , H03K5/15 , H03K19/0948
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公开(公告)号：DE102006047219A1
公开(公告)日：2007-05-24
申请号：DE102006047219
申请日：2006-10-05
Applicant: DENSO CORP
Inventor： TERAZAWA TOMOHITO , WATANABE TAKAMOTO
Abstract: In an analog-to-digital converter, a generating unit executes analog-to-digital conversion of a first input signal and a second input signal based on an analog-to-digital conversion characteristic curve to generate first digital data and second digital data respectively corresponding to the first input signal and the second input signal. The input signal has a first level, and the first level is the sum of an offset level and a level of a target analog signal for analog-to-digital conversion. The second input signal has a second level, and the second level is generated by subtracting the offset level from the level of the target analog signal. In the analog-to-digital converter, an obtaining unit obtains difference digital data between the first digital data and the second digital data to output the obtained difference digital data as digital data of the target analog signal.
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公开(公告)号：DE19509160B4
公开(公告)日：2007-03-22
申请号：DE19509160
申请日：1995-03-14
Applicant: DENSO CORP
Inventor： KANO KAZUHIKO , TAKEUCHI YUKIHIRO , WATANABE TAKAMOTO , AO KENICHI , KANOSUE MASAKAZU , UENOYAMA HIROFUMI , NARA KENICHI
Abstract: A semiconductor acceleration sensor according to the present invention performs acceleration detection by means of detecting increase or decrease in electrical current flowing between fixed electrodes formed on a semiconductor substrate taking a movable section in a movable state supported on the semiconductor substrate as a gate electrode. Two transistor structures are utilized in this detection. Current between fixed electrodes in one transistor structure increases when the movable section is subjected to acceleration and is displaced. At that time, current between fixed electrodes in the other transistor structure decreases. These two transistor structures are disposed proximately. By means of this proximate disposition, fluctuations in characteristics of both transistors are reduced, and by means of acceleration detection by differential type, temperature characteristics of the two transistors can be canceled favorably.
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公开(公告)号：DE102004041558A1
公开(公告)日：2005-05-25
申请号：DE102004041558
申请日：2004-08-27
Applicant: DENSO CORP
Inventor： WATANABE TAKAMOTO , NAKAMURA TETSUYA , MASUDA SUMIO
IPC: H03D1/22 , H04L27/00 , H04L27/227 , H04L27/38
Abstract: In a synchronous detection method, an input signal is averaged over at least first and second phase ranges of a target carrier wave within each period thereof to obtain at least first and second moving average values of the input signal within the at least first and second phase ranges, respectively. The first phase range corresponds to a positively oscillating phase range of the target carrier wave, and the second phase range corresponds to a negatively oscillating phase range thereof. A difference between the first and second moving averages is calculated as a detection result of the target carrier wave.
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Patent Agency Ranking
公开(公告)号：DE10318184A1
公开(公告)日：2004-01-15
申请号：DE10318184
申请日：2003-04-22
Applicant: DENSO CORP
Inventor： WATANABE TAKAMOTO , NAKAMURA MITSUO
Abstract: In a device for analog-to-digital converting an input signal, the input signal is applied to a plurality of delay units constituting a pulse delay circuit in order to change a delay time to be given by the delay units. The number of delay units through which a pulse signal has passed during one period of sampling clocks is numerically expressed. The A/D conversion device has a plurality of pulse position numerizing units that is used for A/D conversion. Sampling clocks of which the phases are different from one another are applied to the respective pulse position numerizing units. An adder summates numerical data items produced by the respective pulse position numerizing units so as to generate final numerical data representing a result of A/D conversion.
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公开(公告)号：DE10235062A1
公开(公告)日：2003-02-13
申请号：DE10235062
申请日：2002-07-31
Applicant: DENSO CORP
Inventor： MIZUNO TAMOTSU , WATANABE TAKAMOTO
Abstract: In an A/D conversion apparatus comprising an A/D converter (4) and a digital moving average filter (6) for removing high-frequency signal components, there is provided an analog moving average filter (2) at a first stage. A sampling frequency of the filters (6 and 2) is set to fsd=nxfsa (where n is a positive integer of 1, 2, ---). As a result, it becomes possible to superimpose an unnecessary signal passing area that appears at every frequency of n times the sampling frequency fsd in the filter (6), on an area of infinite attenuation that appears at every frequency of n times the sampling frequency fsa in the filter (2). In the apparatus as a whole, it becomes possible to efficiently attenuate unnecessary high-frequency signal components. It is also possible to obtain a similar effect when a time A/D converter is used in place of the analog moving average filter (2) and the A/D converter (4).
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公开(公告)号：DE10231999A1
公开(公告)日：2003-01-23
申请号：DE10231999
申请日：2002-07-15
Applicant: DENSO CORP
Inventor： WATANABE TAKAMOTO
Abstract: The input voltage is applied to a pair of pulse delay circuits (30,10) which have mutually opposite delay characteristics. The transfer rate ratio of the pulsating signals in the delay circuits, is calculated and the input voltage is converted into numerical data. An Independent claim is included for analog to digital converter.
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公开(公告)号：DE10210000A1
公开(公告)日：2002-10-31
申请号：DE10210000
申请日：2002-03-07
Applicant: DENSO CORP
Inventor： WATANABE TAKAMOTO , ISOMURA HIROHUMI , MORIKAWA KATSUHIRO
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公开(公告)号：JP2010226211A
公开(公告)日：2010-10-07
申请号：JP2009068509
申请日：2009-03-19
Applicant: Denso Corp , 株式会社デンソー
Inventor： TERASAWA TOMOHITO , YAMAUCHI SHIGENORI , WATANABE TAKAMOTO
IPC: H01L21/82 , H03K5/131 , H03K5/14 , H03K19/177
CPC classification number: H03K19/17736 , H03K19/17728
Abstract: PROBLEM TO BE SOLVED: To configure a pulse delay circuit capable of reducing variations in delay time of each delay unit on a programmable logic device.
SOLUTION: In the method for configuring the pulse delay circuit, many cell strings each of which is composed of a plurality of logic cells arranged in a line are formed in an FPGA, and a delay in transmission between two logic cells belonging to the same cell string (hereafter, called as "transmission in the same cell string") is different from a delay in transmission between two logic cells belonging to different cell strings (hereafter, called as "transmission between different cell strings"). When mounting delay units R1 to Rn configuring a straight delay line on the FPGA, these delay units R1 to Tn are manually arranged. Specifically, the delay units R1 to Rn are allocated to n adjacent cell strings CC1 to CCn one by one, and further a delay unit R1 is allocated to the cell string CCi (i=1, 2, ..., n) so that the delay units R1 to Rn are arranged in the connection order.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：配置能够减少可编程逻辑器件上每个延迟单元的延迟时间变化的脉冲延迟电路。 解决方案：在用于配置脉冲延迟电路的方法中，在FPGA中形成由多个排列成一行的逻辑单元组成的许多单元串，属于两个逻辑单元的传输延迟 相同的单元串（以下称为“同一单元串中的传输”）不同于属于不同单元串的两个逻辑单元之间的传输延迟（以下称为“不同单元串之间的传输”）。 当在FPGA上安装延迟单元R1至Rn构成直线延迟线时，这些延迟单元R1至Tn被手动布置。 具体地说，将延迟单元R1〜Rn分别分配给n个相邻的单元串CC1〜CCn，并且将延迟单元R1分配给单元串CCi（i = 1,2，...，n），使得 延迟单元R1至Rn按照连接顺序排列。 版权所有（C）2011，JPO＆INPIT
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