公开(公告)号：DE19747159B4

公开(公告)日：2006-11-23

申请号：DE19747159

申请日：1997-10-24

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/332 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/74 ,  H01L29/744

Abstract: An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

公开(公告)号：GB2318685B

公开(公告)日：2002-01-02

申请号：GB9722653

申请日：1997-10-24

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/28 ,  H01L21/332 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/08

Abstract: An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

公开(公告)号：AU3808101A

公开(公告)日：2001-08-20

申请号：AU3808101

申请日：2001-02-09

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M ,  ARZUMANYAN ARAM ,  SAMMON TIM

IPC: H01L23/12 ,  H01L21/60 ,  H01L21/822 ,  H01L23/31 ,  H01L23/50 ,  H01L27/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/148 ,  H01L29/768 ,  H01L29/80 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L27/082 ,  H01L27/08

Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

公开(公告)号：DE19918198A1

公开(公告)日：1999-12-09

申请号：DE19918198

申请日：1999-04-22

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/336 ,  H01L29/78

Abstract: The MOSFET has an N-type vertical invertible channel (60) between the source (30-33) and drain (D). A gate oxide (25,26) and contact (28,29) extend along the channel to invert its conductivity. The channel has a constant concentration along its full depth.

公开(公告)号：FR2739976B1

公开(公告)日：1999-04-02

申请号：FR9612435

申请日：1996-10-11

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M ,  WAGERS KENNETH

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L21/334 ,  H01L21/328 ,  H01L29/68

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

公开(公告)号：SG60150A1

公开(公告)日：1999-02-22

申请号：SG1997004030

申请日：1997-11-12

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/302 ,  H01L21/223 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L

Abstract: An MOS-gated power semiconductor device is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body or channel region and the source region of each of the cells. A second photolithographic step is aligned to a small central area above the source region of each of the cells or strips, the only critical alignment in the process, and is used to define openings in a protective oxide layer which, in turn, masks the etching of depressions in the substrate surface and the formation of a contact region. An isotropic etch undercuts the protective oxide to expose shoulders at the silicon surface of the chip which surround the etched holes. A conductive layer fills the holes and thus contacts the underlying body regions and overlaps the shoulders surrounding the source regions at the silicon surface. The conductive layer is sintered at a temperature that is sufficiently high to achieve low contact resistance between the metal and body regions but is low enough to be tolerated by the conductive layer.

公开(公告)号：IT1285780B1

公开(公告)日：1998-06-18

申请号：ITMI962099

申请日：1996-10-10

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M ,  WAGERS KENNETH

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

公开(公告)号：BR9508883A

公开(公告)日：1997-12-30

申请号：BR9508883

申请日：1995-08-17

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：CZ62997A3

公开(公告)日：1997-11-12

申请号：CZ62997

申请日：1995-08-17

Applicant: INT RECTIFIER CORP

Inventor： KINZER DANIEL M

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/332 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/739 ,  H01L29/744 ,  H01L29/749 ,  H01L29/78

Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.

公开(公告)号：ITMI960304A1

公开(公告)日：1997-08-18

申请号：ITMI960304

申请日：1996-02-16

Applicant: INT RECTIFIER CORP

Inventor： AJIT JANARDHANAN S ,  KINZER DANIEL M

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78