中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

154 records (took 0.047 seconds)

    Apparatus and method for processing commands in tile-based renderers
    71.
    发明授权
    Apparatus and method for processing commands in tile-based renderers 审中-公开

    公开(公告)号：US10672176B2

    公开(公告)日：2020-06-02

    申请号：US15692951

    申请日：2017-08-31

    Applicant: Intel Corporation

    Inventor： Hema C. Nalluri ,  Balaji Vembu ,  Peter L. Doyle ,  Michael Apodaca ,  Jeffery S. Boles

    IPC: G06T15/00 ,  G06T15/40

    Abstract: An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.

    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING
    76.
    发明申请
    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING 审中-公开

    公开(公告)号：US20190355084A1

    公开(公告)日：2019-11-21

    申请号：US15982693

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T1/20 ,  G06T17/10

    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

    Facilitating efficient graphics command generation and execution for improved graphics performance at computing devices
    79.
    发明授权
    Facilitating efficient graphics command generation and execution for improved graphics performance at computing devices 有权

    公开(公告)号：US09916634B2

    公开(公告)日：2018-03-13

    申请号：US14738703

    申请日：2015-06-12

    Applicant: INTEL CORPORATION

    Inventor： Michael Apodaca ,  David M. Cimini

    IPC: G06T1/20 ,  G06F9/38

    CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/46

    Abstract: A mechanism is described for facilitating efficient graphics command generation and execution for improved graphics performance at computing devices. A method of embodiments, as described herein, includes detecting an application programming interface (API) call to perform a plurality of transactions, where the API call is issued by an application at a first command buffer, where the plurality of transactions include a first set of transactions and a second set of transactions. The method may further include creating a second command buffer and appending the second command buffer to the first command buffer, where creating further includes separating the first set transactions from the second set of transactions. The method may further include executing, via the second command buffer, the first set of transactions, prior to executing the first set of transactions.

Patent Agency Ranking