公开(公告)号：WO1989011732A1

公开(公告)日：1989-11-30

申请号：PCT/US1988001759

申请日：1988-05-24

Applicant: MICRON TECHNOLOGY, INC. ,  TONG, Paul, Chak, Foon ,  LOWREY, Tyler, A. ,  PARKINSON, Ward, D.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/283

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76895

Abstract: Low resistivity interconnects and silicided N+/P+ active area are formed by sputtering a blanket layer of titanium (33) onto a wafer (13) surface which has the interconnection pattern defined by a thin polysilicon layer (29). A thin oxide layer (27) underneath the polysilicon (29) interconnection pattern serves as an etch stop in the local interconnect photo/etch step. This unprotected oxide layer remaining on top of the N+/P+ active area will be removed by a wet etch prior to the sputtering step. Titanium is then sintered, resulting in conversion of titanium to TiSi2 and TiN. Unreacted titanium and TiN are removed and the remaining TiSi2 provides silicided N+/P+ junctions and a low resistance interconnect level. Advantages of the invention include a low resistance self-aligned contact procedure for the bitline formation, and elimination of the minimal spacing requirement between access transistors imposed by the traditional non self-aligned contact approach.

Abstract translation: 通过将钛（33）的覆盖层溅射到具有由多晶硅薄层（29）限定的互连图案的晶片（13）表面上而形成低电阻率互连和硅化N + / P +有源区。 在多晶硅（29）互连图案下方的薄氧化物层（27）用作局部互连光刻/蚀刻步骤中的蚀刻停止。 残留在N + / P +有效面积顶部的未保护的氧化物层将在溅射步骤之前通过湿式蚀刻去除。 然后将钛烧结，导致钛转化为TiSi 2和TiN。 去除未反应的钛和TiN，剩余的TiSi 2提供硅化N + / P +结和低电阻互连水平。 本发明的优点包括用于位线形成的低电阻自对准接触程序，以及消除由传统的非自对准接触方法施加的存取晶体管之间的最小间隔要求。

公开(公告)号：WO1998036446A2

公开(公告)日：1998-08-20

申请号：PCT/US1997017711

申请日：1997-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  GILGEN, Brent

IPC: H01L21/28

CPC classification number: H01L45/06 ,  G11C2213/52 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.

Abstract translation: 公开了一种用于硫族化物记忆体的电极结构。 电极具有基本截头圆锥形状，并且优选地通过在氧化物图案下方蚀刻蚀刻多晶硅层来形成。 通过这种结构，可以实现通过硫族化物材料的改善的电流密度。

公开(公告)号：WO1998020495A1

公开(公告)日：1998-05-14

申请号：PCT/US1997019967

申请日：1997-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  RUPP, James, P.

IPC: G11C08/00

CPC classification number: G11C29/34 ,  G11C8/04 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: A row decoder circuit operates in a memory integrated circuit, such as a dynamic random access memory (DRAM), having an array of memory cells including row and columns. An address decode tree circuit receives address signals and provides decode signals being activated based on the state of the address signals. Row line driver circuits receive corresponding ones of the decode signals and an enable signal. Each row line driver circuit fires a corresponding row line when the enable signal is activated and the corresponding one of the decode signals is activated. Delay circuitry delays certain of the address signals to stagger the activation of certain of the decode signals to permit multiple row lines to fire in a single row address strobe (RAS) cycle.

Abstract translation: 行解码器电路在具有包括行和列的存储器单元阵列的存储器集成电路（例如动态随机存取存储器（DRAM））中操作。 地址解码树电路接收地址信号，并根据地址信号的状态提供被激活的解码信号。 行线驱动电路接收对应的解码信号和使能信号。 当使能信号被激活并且对应的一个解码信号被激活时，每行行驱动电路触发相应的行线。 延迟电路延迟某些地址信号以使某些解码信号的激活错开以允许多行行在单行地址选通（RAS）周期中触发。

公开(公告)号：WO1998018159A1

公开(公告)日：1998-04-30

申请号：PCT/US1997019054

申请日：1997-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HUDSON, Guy, F.

IPC: H01L21/321

CPC classification number: B24B37/245 ,  H01L21/02024 ,  H01L21/31053 ,  H01L21/3212

Abstract: A method for chemical-mechanical planarization of a substrate on a fixed-abrasive polishing pad in which a planarizing solution is dispensed onto the fixed-abrasive polishing pad. The planarizing solution is preferably an abrasive-free planarizing solution that oxidizes a surface layer on the substrate without passing the surface layer into solution, and the fixed-abrasive pad has a substantially uniform distribution of abrasive particles fixedly bonded to a suspension medium. The surface layer of the substrate is then pressed against the fixed-abrasive pad in the presence of planarizing solution, and at least one of the fixed-abrasive pad or the substrate moves relative to the other to remove material from the surface of the substrate. In operation, the planarizing solution forms a rough, scabrous layer of non-soluble oxides on the surface layer that are readily removed by the abrasive surface of the polishing pad. In one embodiment of the invention, the pH of the planarizing solution is controlled to oxidize the material of the surface layer without passing it into solution.

Abstract translation: 一种用于固定研磨抛光垫上的基板的化学机械平面化的方法，其中将平坦化溶液分配到固定研磨抛光垫上。 平坦化溶液优选是无磨蚀的平坦化溶液，其将基材上的表面层氧化而不使表面层进入溶液，并且固定研磨垫具有固定地结合到悬浮介质上的磨料颗粒的基本上均匀的分布。 然后在平坦化溶液存在的情况下将衬底的表面层压在固定研磨垫上，固定研磨垫或衬底中的至少一个相对于另一个移动，以从衬底的表面移除材料。 在操作中，平坦化溶液在表面层上形成粗糙，粗糙的不可溶性氧化物层，其易于被抛光垫的磨料表面除去。 在本发明的一个实施方案中，平面化溶液的pH被控制以氧化表面层的材料，而不将其转化为溶液。

公开(公告)号：WO1998018134A1

公开(公告)日：1998-04-30

申请号：PCT/US1997018734

申请日：1997-10-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SHER, Joseph, C. ,  MERRITT, Todd, A.

IPC: G11C29/00

CPC classification number: G01R31/31701 ,  G11C29/46

Abstract: A supervoltage circuit has been described which uses a resistor divider as an input stage. The resistor divider decreases the dependency of the supervoltage trip point on transistor threshold voltages (Vt). The stability of supervoltage trip point is significantly increased over traditional supervoltage circuits using diode connected transistors as an input stage. The supervoltage circuit can be included in any integrated circuit including memory devices.

Abstract translation: 已经描述了使用电阻分压器作为输入级的超压电路。 电阻分压器降低了超级电压跳变点对晶体管阈值电压（Vt）的依赖性。 与使用二极管连接的晶体管作为输入级的传统超压电路相比，超级电压跳变点的稳定性显着提高。 超级电路可以包括在包括存储器件的任何集成电路中。

公开(公告)号：WO1998018130A1

公开(公告)日：1998-04-30

申请号：PCT/US1997018941

申请日：1997-10-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PAWLOWSKI, J., Thomas

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: A dynamic memory (14) having a refresh control circuit (18) is comprised of a main array (15) of memory cells organized according to addresses. A first circuit (16, 41) is provided for performing external operations on addresses within the main array (15) of memory cells. A refresh data memory array (20) and a timing circuit (30) for producing timing information (32) related to the refresh rate of the cells of the main array (15) are provided. A write driver circuit (34) is responsive to a refresh signal (43) and a request for the performance of an external operation on a selected address in the main array (15) for writing a portion of the timing information (32) to the refresh data memory array (20) according to addresses corresponding to addresses used in the main array. A counter (36) generates a plurality of addresses and a second circuit (40), responsive to the generated addresses, reads the written portion of the timing information from the refresh data array (20). A logic circuit (42) is responsive to the portion of the timing information read from the refresh data array and the then current value of the timing information for producing the refresh signal (43) indicative of when a refresh is required. An arbitration circuit (48, 50, 56) selects either the refresh signal (43) or the request for the performance of an external operation. Select circuits (38, 39) are responsive to the arbitration circuit (48, 50, 56) for selectively conducting either the generated address or the selected address to row decoders (40, 41) within the first and second circuits to ensure that the main array (15) of memory cells and the refresh data memory array (20) are being operated upon at the same address. A method of intelligently refreshing a dynamic memory is also enclosed.

Abstract translation: 具有刷新控制电路（18）的动态存储器（14）由根据地址组织的存储器单元的主阵列（15）组成。 提供第一电路（16,41），用于对存储器单元的主阵列（15）内的地址执行外部操作。 提供了用于产生与主阵列（15）的单元的刷新率相关的定时信息（32）的刷新数据存储器阵列（20）和定时电路（30）。 写入驱动器电路（34）响应于刷新信号（43）和对主阵列（15）中的选定地址执行外部操作的请求，用于将定时信息（32）的一部分写入到 根据与主阵列中使用的地址对应的地址刷新数据存储器阵列（20）。 计数器（36）产生多个地址，并且响应于所产生的地址的第二电路（40）从刷新数据阵列（20）读取定时信息的写入部分。 逻辑电路（42）响应于从刷新数据阵列读出的定时信息的一部分和用于产生刷新信号（43）的定时信息的当前值，该刷新信号指示何时需要刷新。 仲裁电路（48,50,56）选择刷新信号（43）或执行外部操作的请求。 选择电路（38,39）响应仲裁电路（48,50,56），用于选择性地将所生成的地址或所选择的地址传送到第一和第二电路内的行解码器（40,41），以确保主 存储器单元的阵列（15）和刷新数据存储器阵列（20）正在同一地址上操作。 还包括智能地刷新动态存储器的方法。

公开(公告)号：WO1998007161A1

公开(公告)日：1998-02-19

申请号：PCT/US1997014086

申请日：1997-08-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MERRITT, Todd, A.

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G01R31/31702

Abstract: A semiconductor integrated circuit includes a plurality of programmable elements such as antifuses (16, 17), each having a first terminal connected to a first power supply potential (CGND) and a second terminal. Each of a plurality of first semiconductor switching elements (18, 19) has a first terminal respectively connected to the second terminal of a corresponding one of the plurality of programmable elements and has a second terminal. Each of a plurality of second semiconductor switching elements (20) has a first terminal connected in common to selected ones of the second terminals of the plurality of first semiconductor switching elements and has a second terminal connected to a second power supply potential. A method of programming a plurality of programmable elements grouped in a plurality of subgroups each in a respective one of a plurality of groups includes the steps of applying a programming signal to the subgroups in a respective one of the groups and applying an address signal at like respective terminals in each of said groups, with each which terminal there is associated one of said programmable elements, either the programming signal or the address signal being applied by a common switching element.

Abstract translation: 半导体集成电路包括多个可编程元件，例如反熔丝（16,17），每个具有连接到第一电源电位（CGND）的第一端子和第二端子。 多个第一半导体开关元件（18,19）中的每一个具有分别连接到多个可编程元件中的对应的一个的第二端子的第一端子并具有第二端子。 多个第二半导体开关元件（20）中的每一个具有与多个第一半导体开关元件中的选定的第二端子共同连接的第一端子，并且具有连接到第二电源电位的第二端子。 将分组在多个子组中的多个子组中的多个可编程元件编程在多个组中的相应一个组中的方法包括以下步骤：将编程信号施加到组中的相应组中的子组并且以类似的方式施加地址信号 每个所述组中的各个终端，其中每个终端与所述可编程元件中的一个相关联，编程信号或地址信号由公共开关元件施加。

公开(公告)号：WO1998005070A1

公开(公告)日：1998-02-05

申请号：PCT/US1997013498

申请日：1997-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MANNING, Monte

IPC: H01L27/11

CPC classification number: H01L27/11

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.

Abstract translation: 描述了具有交叉耦合下拉晶体管和双重存取晶体管的静态存储单元。 存储单元被制造成使得通过两个下拉晶体管形成平衡电流路径。 单个字线用于激活将存储器单元耦合到互补位线的存取晶体管。 如平面图所示，存储单元具有并行制造的下拉晶体管的单个字线和栅极。

公开(公告)号：WO1997048048A1

公开(公告)日：1997-12-18

申请号：PCT/US1997010184

申请日：1997-06-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PAWLOWSKI, Joseph, Thomas

IPC: G06F12/08

CPC classification number: G06F11/1064 ,  G06F12/0879 ,  G06F12/0886

Abstract: A logic which enables implementation of an 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by merging tag, and data into an order block of information to maximize bus utilization. The logic reduces the bus cycles from four cycles for an 80-bit to three cycles for a 96-bit implementation.

Abstract translation: 这是一种使用相同存储器阵列实现80位宽或96位宽缓存SRAM的逻辑。 逻辑实现通过将标签和数据合并到信息的顺序块中来实现，以最大化总线利用率。 该逻辑从96位实现的80位到3个周期的四个周期中减少总线周期。

公开(公告)号：WO1997045872A1

公开(公告)日：1997-12-04

申请号：PCT/US1997009238

申请日：1997-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SHER, Joseph, C. ,  SMITH, Eric, J.

IPC: H01L23/525

CPC classification number: G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A programming circuit for an anti-fuse utilizes a boot circuit that charges a capacitor to the supply voltage during a non-programming period. Anti-fuse is to be programmed, the plate of the capacitor to which the supply voltage has been applied is switched to 0 volt, thereby causing the other plate of the capacitor to output a negative voltage. This negative voltage is switched to one plate of an anti-fuse, and the other plate of the anti-fuse receives a positive voltage from an external source. A voltage is thereby applied across the anti-fuse that is greater than any voltage applied to any node of the integrated circuit.

Abstract translation: 用于反熔丝的编程电路利用在非编程周期期间将电容器充电到电源电压的引导电路。 要对编程的保险丝进行编程，将施加电源电压的电容器的电容切换为0伏，从而使电容器的另一个电极输出负电压。 该负电压切换到一个反熔丝板，反熔丝的另一个板从外部电源接收正电压。 因此，跨过反熔丝施加的电压大于施加到集成电路的任何节点的任何电压。