公开(公告)号：WO1998005070A1

公开(公告)日：1998-02-05

申请号：PCT/US1997013498

申请日：1997-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MANNING, Monte

IPC: H01L27/11

CPC classification number: H01L27/11

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.

Abstract translation: 描述了具有交叉耦合下拉晶体管和双重存取晶体管的静态存储单元。 存储单元被制造成使得通过两个下拉晶体管形成平衡电流路径。 单个字线用于激活将存储器单元耦合到互补位线的存取晶体管。 如平面图所示，存储单元具有并行制造的下拉晶体管的单个字线和栅极。

公开(公告)号：EP0916159B1

公开(公告)日：2005-09-21

申请号：EP97938082.1

申请日：1997-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MANNING, Monte

IPC: H01L27/11

CPC classification number: H01L27/11

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.

Abstract translation: 描述了具有交叉耦合的下拉晶体管和双存取晶体管的静态存储器单元。 存储器单元被制造为使得通过两个下拉晶体管形成平衡电流路径。 单字线用于激活将存储单元耦合到互补位线的存取晶体管。 如平面图所示，存储器单元具有并行制造的下拉晶体管的单字线和栅极。

公开(公告)号：EP0916159A1

公开(公告)日：1999-05-19

申请号：EP97938082.0

申请日：1997-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MANNING, Monte

IPC: G11C11 ,  H01L21 ,  H01L27

CPC classification number: H01L27/11

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.