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公开(公告)号：MY114958A
公开(公告)日：2003-02-28
申请号：MYPI9804177
申请日：1998-09-11
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH S , YOUNIS SAED G
Abstract: A BANDPASS ( ) ADC UTILISES EITHER A SINGLE-LOOP (10) OR A MASH ARCHITECTURE (12, 100, 121). RESONATORS ARE IMPLEMENTED AS EITHER A DELAY CELL RESONATOR (131), A LOSSLESS DISCRETE INTEGRATOR RESONATOR (132), A FORWARD-EULER RESONATOR (133), OR A TWO-PATH INTERLEAVED RESONATOR (134). THE RESONATOR CAN BE SYNTHESIZED WITH ANALOG CIRCUIT TECNIQUES SUCH AS ACTIVE-RC, GM-C, MOSFET-C, SWITCHED CAPACITOR, OR SWITCHED CAPACITOR, OR SWITCHED CURRENT. THE SWITCHED CAPACITOR OR SWITCHED CURRENT CIRCUITS CAN BE DESIGNED USING-SAMPLING, DOUBLE-SAMPLING, OR MULTI-SAMPLING CIRCUITS. THE NON-STRINGENT REQUIREMENT OF A ( ) ADC USING SWITCHED CAPACITOR CIRCUITS ALLOWS THE ADC TO BE IMPLEMENTED IN A CMOS PROCESS TO MINIMIZE COST AND REDUCE POWER CONSUMPTION. DOUBLE-SAMPLING CIRCUIT (101) PROVIDE IMPROVED MATCHING AND IMPROVED TOLERANCE TO SAMPLING CLOCK JITTER. IN PARTICULAR, A BANDPASS MASH 4-4( ) ADC PROVIDES A SIMULATED SIGNAL-TO-NOISE RATIO OF 85DB AT AN OVERSAMPLING RATIO OF 32 FOR A CDMA APPLICATION. THE BANDPASS ( ) ADC CAN ALSO BE USED IN CONJUNTION WITH UNDERSAMPLING TO PROVIDE A FREQUENCY DOWNCONVERSION.
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公开(公告)号：MY114831A
公开(公告)日：2003-01-31
申请号：MYPI9805485
申请日：1998-12-03
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH S , CICCARELLI STEVEN C , YOUNIS SAED G , BUTTERFIELD DANIEL K
Abstract: A RECEIVER(2200) COMPRISING A SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER (EA ADC) CAN BE UTILIZED IN ONE OF FOUR CONFIGURATION, AS A SUBSAMPLING BANDPASS RECEIVER, A SUBSAMPLING BASEBAND RECEIVER, A NYQUIST SAMPLING BANDPASS RECEIVER, OR A NYQUIST SAMPLING BASEBAND RECEIVER. FOR SUBSAMPLING EA RECEIVERS, THE SAMPLING FREQUENCY IS LESS THAN TWICE THE CENTER FREQUENCY OF THE INPUT SIGNAL INTO THE EA ADC. FOR NYQUIST SAMPLING EA RECEIVERS, THE SAMPLING FREQUENCY IS AT LEAST TWICE THE HIGHEST FREQUENCY OF THE INPUT SIGNAL INTO THE EA ADC. FOR BASEBAND AE RECEIVERS, THE CENTER FREQUENCY OF THE OUTPUT SIGNAL FROM THE EA ADC IS GREATER THAN ZERO. THE SAMPLING FREQUENCY CAN BE SELECTED BASED ON THE BANDWIDTH OF THE INPUT SIGNAL TO SIMPLIFY THE DESIGN OF THE DIGITAL CIRCUITS USED TO PROCESS THE OUTPUT SAMPLES FROM THE EA ADC. FURTHERMORE, THE CENTER FREQUINCY OF THE INPUT SIGNAL CAN BE SELECTED BASED ON THE SAMPLING FREQUINCY AND THE BANDWIDTH OF THE INPUT SIGNAL. THE EA ADC WITHIN THE RECEIVER PROVIDES MANY BENEFITS.FIG 2
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公开(公告)号：AU754973B2
公开(公告)日：2002-11-28
申请号：AU1632999
申请日：1998-12-08
Applicant: QUALCOMM INC
Inventor： CICCARELLI STEVEN C , YOUNIS SAED G , KAUFMAN RALPH E
Abstract: A programmable linear receiver which provides the requisite level of system performance at reduced power consumption. The receiver minimizes power consumption based on measurement of the non-linearity in the output signal from the receiver. The amount of non-linearity can be measured by the RSSI slope or energy-per-chip-to-noise-ratio (Ec/Io) measurement. The RSSI slope is the ratio of the change in the output signal plus intermodulation to the change in the input signal. The input signal level is periodically increased by a predetermined level and the output signal from the receiver is measured. The output signal comprises the desired signal and intermodulation products from non-linearity within the receiver. When the receiver is operating linearly, the output signal level increases dB per dB with the input signal level. However, as the receiver transitions into non-linear region, intermodulation products due to non-linearity increase faster than the desired signal. By detecting the RSSI slope, the amount of degradation due to non-linearity can be determined. This information is then used to adjust the IIP3 operating point of the amplifiers and mixer to provide the requisite level of performance while minimizing power consumption.
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公开(公告)号：AU742487B2
公开(公告)日：2002-01-03
申请号：AU9308898
申请日：1998-09-08
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH S , YOUNIS SAED G
IPC: H03M3/02
Abstract: A bandpass SIGMA DELTA DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
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公开(公告)号：CA2406716A1
公开(公告)日：2001-11-15
申请号：CA2406716
申请日：2001-05-08
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G , PATRICK CHRISTOPHER
IPC: G01S1/00 , G01S7/40 , G01S19/03 , G01S19/23 , H03J7/04 , H03L1/00 , H03L1/02 , H03L7/06 , H03L7/18 , H04B1/707 , H04L27/00 , H04B1/26 , H03B1/04 , G01S5/14
Abstract: The frequency error of an oscillator is minimized by characterizing the oscillator. A reference signal from an external source containing a minimal frequency error is provided to an electronic device. The external signal is used as a reference frequency to estimate the frequency error of an internal frequency source. The electronic device monitors parameters that are determined to have an effect on the frequency accuracy of the internal frequency source. Temperature is one parameter known to have an effect on th e frequency of the internal frequency source. The electronic device collects a nd stores the values of the parameters as well as the corresponding output frequency or frequency error of the internal frequency source. The resultant characterization of the internal frequency source is used to compensate the internal frequency source when the internal frequency source is not provided the external reference signal.
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Patent Agency Ranking
公开(公告)号：HK1032160A1
公开(公告)日：2001-07-06
申请号：HK01101395
申请日：2001-02-26
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G , BAZARJANI SEYFOLLAH S , CICCARELLI STEVEN C
IPC: H03M1/18 , H04B20060101 , H03M20060101 , H03M3/02 , H04B1/10 , H04B1/16
Abstract: A programmable dynamic range receiver which provides the requisite level of performance at reduced power consumption. The SIGMA DELTA ADC within the receiver is designed with one or more loops. Each loop provides a predetermined dynamic range performance. The loops can be enabled or disabled based on the required dynamic range and a set of dynamic range thresholds. The SIGMA DELTA ADC is also designed with adjustable bias current. The dynamic range of the SIGMA DELTA ADC varies approximately proportional to the bias current. By adjusting the bias current, the required dynamic range can be provided by the SIGMA DELTA ADC with minimal power consumption. A reference voltage of the SIGMA DELTA ADC can be descreased when high dynamic range is not required, thereby allowing for less bias current in the SIGMA DELTA ADC and supporting circuitry. The dynamic range of the SIGMA DELTA ADC is a also function of the oversampling ratio which is proportional to the sampling frequency. High dynamic range requires a high oversampling ratio. When high dynamic range is not required, the sampling frequency can be lowered.
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公开(公告)号：BR9908440A
公开(公告)日：2000-12-05
申请号：BR9908440
申请日：1999-03-02
Applicant: QUALCOMM INC
Inventor： CICCARELLI STEVEN C , YOUNIS SAED G
IPC: G01S19/07 , G01S19/11 , G01S19/12 , G01S19/31 , H04B1/26 , H04B1/38 , H04B1/40 , H04B1/62 , H04L27/22
Abstract: A receiver that downconverts input signals modulated using first, second, third and fourth modulation formats to a common intermediate frequency range. The first and second modulation formats are transmitted to the receiver in a first frequency range, the third modulation format is transmitted to the receiver in a second frequency range, and the fourth modulation format is transmitted to the receiver in a third frequency range. The input signals are provided to first, second and third band selection filters that respectively select first, second and third frequency ranges. A first downconverter is coupled to an output of the first band selection filter, and downconverts signals from the first frequency range to the common intermediate frequency range. A second downconverter is selectively coupled by a switch to either an output of the second band selection filter or an output of the third band selection filter, and downconverts signals from either the second frequency range or the third frequency range to the common intermediate frequency range. The second downconverter has an input coupled to a frequency doubling circuit. Switching circuitry selectively couples one of either a first oscillating signal from a voltage controlled oscillator (VCO) having a VCO frequency range or a second oscillating signal at a second frequency that is outside the VCO frequency range to an input of the first downconverter and an input of the frequency doubling circuit.
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公开(公告)号：BR9813483A
公开(公告)日：2000-11-14
申请号：BR9813483
申请日：1998-12-08
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G , BAZARJANI SEYFOLLAH S , CICCARELLI STEVEN C
Abstract: A programmable dynamic range receiver which provides the requisite level of performance at reduced power consumption. The SIGMA DELTA ADC within the receiver is designed with one or more loops. Each loop provides a predetermined dynamic range performance. The loops can be enabled or disabled based on the required dynamic range and a set of dynamic range thresholds. The SIGMA DELTA ADC is also designed with adjustable bias current. The dynamic range of the SIGMA DELTA ADC varies approximately proportional to the bias current. By adjusting the bias current, the required dynamic range can be provided by the SIGMA DELTA ADC with minimal power consumption. A reference voltage of the SIGMA DELTA ADC can be descreased when high dynamic range is not required, thereby allowing for less bias current in the SIGMA DELTA ADC and supporting circuitry. The dynamic range of the SIGMA DELTA ADC is a also function of the oversampling ratio which is proportional to the sampling frequency. High dynamic range requires a high oversampling ratio. When high dynamic range is not required, the sampling frequency can be lowered.
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公开(公告)号：ZA9811125B
公开(公告)日：2000-10-10
申请号：ZA9811125
申请日：1998-12-04
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH S , CICCARELLI STEVEN C , YOUNIS SAED G , BUTTERFIELD DANIEL K
Abstract: A receiver comprising a sigma-delta analog-to-digital converter ( SIGMA DELTA ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling SIGMA DELTA receivers, the sampling frequency is less than twice the center frequency of the input signal into the SIGMA DELTA ADC. For Nyquist sampling SIGMA DELTA receivers, the sampling frequency is at least twice the highest frequency of the input signal into the SIGMA DELTA ADC. For baseband SIGMA DELTA receivers, the center frequency of the output signal from the SIGMA DELTA ADC is approximately zero or DC. For bandpass SIGMA DELTA receivers, the center frequency of the output signal from the SIGMA DELTA ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the SIGMA DELTA ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The SIGMA DELTA ADC within the receiver provides many benefits.
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80.发明专利
公开(公告)号：AU2182100A
公开(公告)日：2000-07-03
申请号：AU2182100
申请日：1999-12-14
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G , BUTTERFIELD DANIEL KEYES
IPC: H03M3/02
Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention eliminates the clock jitter disadvantage between sampled-data and Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter preferably includes at least two switches and a capacitor. A first switch is used to charge the capacitor and a second switch is used to discharge the capacitor. Each switch is controlled by a clock phase wherein the sum of the two phases equals the clock duty cycle.
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