公开(公告)号：JP2009290886A

公开(公告)日：2009-12-10

申请号：JP2009176424

申请日：2009-07-29

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H04B1/40 ,  H03F3/24 ,  H04B1/38 ,  H04L27/00

CPC classification number: H03F3/24 ,  H03F2200/331 ,  H04B1/40

Abstract: PROBLEM TO BE SOLVED: To provide a hardware-efficient transceiver with a delta-sigma digital-to-analog converter. SOLUTION: The present invention relates to a hardware-efficient transceiver. A transceiver 80 includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer 84 provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter 82 converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供具有delta-sigma数模转换器的硬件高效收发器。 解决方案：本发明涉及一种硬件高效收发器。 收发器80包括用于将基带信号转换成中频信号的数字电路。 信号源提供第一频率的第一周期信号。 直接数字合成器84从第一周期性参考信号提供第二频率的第二周期信号。 上变频器电路使用第二周期信号将基带信号数字上变频到数字中频信号。 数模转换器82使用第一周期信号将数字中频信号转换成模拟中频信号。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2013153447A

公开(公告)日：2013-08-08

申请号：JP2013024945

申请日：2013-02-12

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H04B1/40 ,  H03F3/24 ,  H04B1/38 ,  H04L27/00

CPC classification number: H03F3/24 ,  H03F2200/331 ,  H04B1/40

Abstract: PROBLEM TO BE SOLVED: To provide a hardware-efficient transceiver with a delta-sigma digital-to-analog converter.SOLUTION: A hardware-efficient transceiver 80 includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer 84 provides a second periodic signal of a second frequency from a first periodic reference signal. An upconverter circuit 98, 100 digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter 82 converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.

Abstract translation: 要解决的问题：提供具有Δ-Σ数字 - 模拟转换器的硬件高效收发器。解决方案：硬件高效收发器80包括用于将基带信号转换为中频信号的数字电路。 信号源提供第一频率的第一周期信号。 直接数字合成器84从第一周期性参考信号提供第二频率的第二周期信号。 上变频器电路98,100使用第二周期信号将基带信号数字上变频到数字中频信号。 数模转换器82使用第一周期信号将数字中频信号转换成模拟中频信号。

公开(公告)号：JP2013118690A

公开(公告)日：2013-06-13

申请号：JP2013024942

申请日：2013-02-12

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H04B1/40 ,  H03F3/24 ,  H04B1/04 ,  H04B1/26 ,  H04B1/38 ,  H04L27/00

CPC classification number: H03F3/24 ,  H03F2200/331 ,  H04B1/40

Abstract: PROBLEM TO BE SOLVED: To provide a hardware-efficient transceiver with a delta-sigma digital-to-analog converter.SOLUTION: Provided is a hardware-efficient transceiver. A transceiver 80 includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer 84 provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter 82 converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.

Abstract translation: 要解决的问题：提供具有delta-sigma数模转换器的硬件高效收发器。

解决方案：提供了一种硬件高效的收发器。 收发器80包括用于将基带信号转换成中频信号的数字电路。 信号源提供第一频率的第一周期信号。 直接数字合成器84从第一周期性参考信号提供第二频率的第二周期信号。 上变频器电路使用第二周期信号将基带信号数字上变频到数字中频信号。 数模转换器82使用第一周期信号将数字中频信号转换成模拟中频信号。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012055005A

公开(公告)日：2012-03-15

申请号：JP2011246460

申请日：2011-11-10

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H04B1/40 ,  H03F3/24 ,  H04B1/38 ,  H04L27/00

CPC classification number: H03F3/24 ,  H03F2200/331 ,  H04B1/40

Abstract: PROBLEM TO BE SOLVED: To provide a hardware-efficient transceiver with delta-sigma digital-to-analog converter.SOLUTION: There is provided a hardware-efficient transceiver. The transceiver 80 includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer 84 provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter 82 converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.

Abstract translation: 要解决的问题：提供具有delta-sigma数模转换器的硬件高效收发器。

解决方案：提供了一个硬件高效收发器。 收发器80包括用于将基带信号转换成中频信号的数字电路。 信号源提供第一频率的第一周期信号。 直接数字合成器84从第一周期性参考信号提供第二频率的第二周期信号。 上变频器电路使用第二周期信号将基带信号数字上变频到数字中频信号。 数模转换器82使用第一周期信号将数字中频信号转换成模拟中频信号。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：CA2354623A1

公开(公告)日：2000-06-22

申请号：CA2354623

申请日：1999-12-14

Applicant: QUALCOMM INC

Inventor： YOUNIS SAED G ,  BUTTERFIELD DANIEL KEYES

IPC: H03M3/02

Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter (15) using a Continuous-Time implementation having suppressed sensitivity to cloc k jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter (17) that ensure s that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter (17) preferably includes at least two switches and a capacitor (28).

公开(公告)号：AU5323299A

公开(公告)日：2000-02-21

申请号：AU5323299

申请日：1999-07-27

Applicant: QUALCOMM INC

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H03F3/24 ,  H04B1/38 ,  H04B1/40 ,  H04L27/00 ,  H04B1/00

Abstract: A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal. Transmit and receive circuitry are provided for transmitting the analog transmit signal and receiving an analog receive signal, respectively. In a specific embodiment, the analog receive signal is digitally downconverted to provide a digital receive signal in response to a second periodic signal. A significant feature of the invention resides in the provision of the first and second periodic signals with a single local oscillator. A direct digital synthesizer is included for generating one of the reference signals from the output of the local oscillator. The transmit circuit includes a delta-sigma digital-to-analog converter having the first periodic signal as an input The delta-sigma digital-to-analog converter has a low-bit digital-to-analog converter and a delta-sigma modulator. In the illustrative embodiment, the low-bit digital-to-analog converter is a 1-bit digital-to-analog converter and the delta-sigma modulator is a sixth order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.

公开(公告)号：CA2338539C

公开(公告)日：2010-11-30

申请号：CA2338539

申请日：1999-07-27

Applicant: QUALCOMM INC

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H04B1/00 ,  H03F3/24 ,  H04B1/38 ,  H04B1/40 ,  H04L27/00

Abstract: A hardware-efficient transceiver. The transceiver (80) includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer (84) provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal. A digital-to-analog converter converts (82) the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal.

公开(公告)号：BR9912530A

公开(公告)日：2001-10-23

申请号：BR9912530

申请日：1999-07-27

Applicant: QUALCOMM INC

Inventor： BUTTERFIELD DANIEL KEYES

IPC: H03M3/02 ,  H03F3/24 ,  H04B1/38 ,  H04B1/40 ,  H04L27/00 ,  H04B1/00

Abstract: A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal. Transmit and receive circuitry are provided for transmitting the analog transmit signal and receiving an analog receive signal, respectively. In a specific embodiment, the analog receive signal is digitally downconverted to provide a digital receive signal in response to a second periodic signal. A significant feature of the invention resides in the provision of the first and second periodic signals with a single local oscillator. A direct digital synthesizer is included for generating one of the reference signals from the output of the local oscillator. The transmit circuit includes a delta-sigma digital-to-analog converter having the first periodic signal as an input The delta-sigma digital-to-analog converter has a low-bit digital-to-analog converter and a delta-sigma modulator. In the illustrative embodiment, the low-bit digital-to-analog converter is a 1-bit digital-to-analog converter and the delta-sigma modulator is a sixth order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.

公开(公告)号：AU2182100A

公开(公告)日：2000-07-03

申请号：AU2182100

申请日：1999-12-14

Applicant: QUALCOMM INC

Inventor： YOUNIS SAED G ,  BUTTERFIELD DANIEL KEYES

IPC: H03M3/02

Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention eliminates the clock jitter disadvantage between sampled-data and Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter preferably includes at least two switches and a capacitor. A first switch is used to charge the capacitor and a second switch is used to discharge the capacitor. Each switch is controlled by a clock phase wherein the sum of the two phases equals the clock duty cycle.

公开(公告)号：ES2391714T3

公开(公告)日：2012-11-29

申请号：ES09790669

申请日：2009-07-21

Applicant: QUALCOMM INC

Inventor： GARUDADRI HARINATH ,  MAJUMDAR SOMDEB ,  BUTTERFIELD DANIEL KEYES ,  TANG YI ,  MARTHANDA SANJAY

IPC: H03F3/217

Abstract: Un aparato, que comprende:un medio (106, 200) para cuantificar una señal, en el que el medio para cuantificar la señal consta de tresniveles; yun medio (108, 302) para excitar una carga (110) que tiene bornes primero y segundo, en el que el mediopara excitar la carga está configurado para conmutar los bornes primero y segundo entre carriles de alimentaciónprimero y segundo solamente si la salida del cuantificador se encuentra en uno de los tres niveles, yen el que el medio para excitar una carga está configurado, además, para conmutar los bornes primero ysegundo entre los carriles de alimentación primero y segundo con un ciclo de trabajo ajustable.