WIRING FORMING METHOD AND ECR ETCHING APPARATUS USED FOR THE SAME

    公开(公告)号:JPH04336422A

    公开(公告)日:1992-11-24

    申请号:JP10761591

    申请日:1991-05-13

    Applicant: SONY CORP

    Abstract: PURPOSE:To easily form tungsten plug wiring only within a contact hole by forming a reaction seed film which will become a reaction seed for tungsten only within a contact hole on a semiconductor substrate. CONSTITUTION:A tungsten silicide (WSix) film 6, which will become a reaction seed film for CVD growth of selected tungsten, is formed in the thickness of 50nm. Next, the WSix film 6 is anisotropically etched to form a reaction seed (WSix) film 6a by leaving a part in the height of 0.4mum within a contact hole 4. In this case, a wafer (Si substrate 1) is inclined by about 45 degrees. Next, a tungsten plug wiring 7 is selectively grown by the CVD method under the reduced pressure condition on the reaction seed (WSix) film 6a and only within the contact hole 4.

    METHOD OF FORMING PLUG OF BLANKET TUNGSTEN

    公开(公告)号:JPH04288824A

    公开(公告)日:1992-10-13

    申请号:JP5271591

    申请日:1991-03-18

    Applicant: SONY CORP

    Abstract: PURPOSE:To provide a method for forming plugs of blanket tungsten having low contact resistance and good step coverage. CONSTITUTION:A heat-resistant layer 3 is formed in some positions on a silicon substrate 1 where a plug is to be made, and an insulating film 4 is formed on the whole surface. Then a contact hole 5 for exposing the above-mentioned heat resisting layer surface is bored in the above-mentioned insulating film 4, and a silicon-based film 6 is formed on the exposed surface. Next the above- mentioned contact hole is filled up by depositing blanket tungsten on the whole surface, and a tungsten layer 8 is formed.

    FIELD EMISSION TYPE EMITTER AND MANUFACTURE THEREOF

    公开(公告)号:JPH04167326A

    公开(公告)日:1992-06-15

    申请号:JP29318490

    申请日:1990-10-30

    Applicant: SONY CORP

    Abstract: PURPOSE:To strengthen a gate electrode in structure to prevent inferior insulation between a cathode and the gate electrode by forming side walls of an insulating film at a cavity part of a field emission type emitter into a reverse tapered shape. CONSTITUTION:An insulating film 2 is formed on a conductive substrate 1, and a cavity 2a formed on the film 2, a cathode 3 formed on the substrate 1 inside the cavity 2a, and a gate electrode 4 formed on the film 2 are provided. Side walls of the film 2 at the part of the cavity 2 are formed into a reverse tapered shape. Since the structure is thereby made such that nearly all portions of the electrode 4 are supported by the film 2, the electrode can be structurally strengthened. Accordingly, the electrode 4 can not be peeled off from the film 2. Since a bottom portion diameter of the cavity 2 is larger than an upper portion diameter thereof, the cathode 3 can be formed into a suitable shape so as to prevent inferior insulation between the cathode 3 and the electrode 4.

    METHOD OF FORMING INTERCONNECTION
    74.
    发明专利

    公开(公告)号:JPH04120725A

    公开(公告)日:1992-04-21

    申请号:JP24140590

    申请日:1990-09-12

    Applicant: SONY CORP

    Abstract: PURPOSE:To improve the morphology of refractory metal and obtain interconnections with good step coverage by forming an adhesive layer in a contact hole, forming a thin silicon on the adhesive layer, substituting refractory metal for the silicon film, and further depositing refractory metal. CONSTITUTION:A contact hole is opened in an inner insulating film 2 on a diffused region 1a that is formed in a p-type silicon substrate 1, so that the diffused region is exposed. Titanium nitride 3 is deposited on the wall of the contact hole 2a and the exposed insulating film 2. Then, polysilicon film 4 is deposited on the titanium nitride film 3. The polysilicon film is substituted with a tungsten film 5 through the reduction of WF6 by Si. This reductive reaction is carried out until the silicon disappears, and then another tungsten film 6 is deposited on the tungsten film 5. As a result, the morphology of the refractory metal is improved and good step coverage is obtained.

    FORMATION OF MULTILAYERED WIRING
    75.
    发明专利

    公开(公告)号:JPH03244131A

    公开(公告)日:1991-10-30

    申请号:JP4184490

    申请日:1990-02-22

    Applicant: SONY CORP

    Abstract: PURPOSE:To make excellent connections by selectively growing upper-lower interconnection metal films in undergrowth, by bevelling hole corners to remove steps, and by filling holes with metal films. CONSTITUTION:A W film 4 is undergrown in a connection hole 3 of an interlayer insulating film 2 over the lower layer wiring by CVD with SiH4 and WF6. Bias ECRCVD is conducted under a condition of SiH4 (7SCCM)/N2O (35SCCM), 7X10 Torr, microwave 1KW, bias RF 0.5KW, and 875 gauss, for example. At this time, a flat face meets etch rate = deposition rate, and a sloped face meets etch rate>deposition rate: a hole 3 is bevelled. The next step of filling a recess up with a W film 7 to flatten the surface allows enlargement of the top area of the W films 4, 7, where the film 7 can be deposited by liquid phase CVD. The final step of forming the upper layer wiring 5 such as of Al can make excellent connections.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    76.
    发明专利

    公开(公告)号:JP2003209111A

    公开(公告)日:2003-07-25

    申请号:JP2002008332

    申请日:2002-01-17

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which forms a fine interconnection using buried interconnection forming techniques without causing the separation or deformation of an interlayer insulation film during processes, and which uses a film of low permittivity having low film strength as the interlayer insulation film. SOLUTION: A trench pattern 4b is formed in an insulation film 4 for processing on a base substrate 1, and a conductive material film 5 is formed on the insulation film 4 for processing so as to fill the trench pattern 4b. Next, the conductive material film 5 is polished until the insulation film 4 for processing is exposed to form interconnections (second interconnections 5b) which are made by filling the trench pattern 4b with the conductive material film 5. Thereafter, the insulation film 4 for processing is removed by etching until side walls of the interconnections 5b are exposed. The interlayer insulation film 6 having low permittivity is formed over the base substrate 1 so as to fill spaces between the interconnection 5b. COPYRIGHT: (C)2003,JPO

    MANUFACTURE OF ELECTRONIC DEVICE
    77.
    发明专利

    公开(公告)号:JP2000183052A

    公开(公告)日:2000-06-30

    申请号:JP36114498

    申请日:1998-12-18

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To enhance an organic dielectric film in adhesion to a work by a method wherein the work is inversely sputtered so as to be provided with dangling bonds on its surface, and then the organic dielectric film is formed thereon. SOLUTION: Dangling bonds are formed on the surface of a work 10 by inverse sputtering. By inverse sputtering, active sites are formed on the surface of the work 10, so that an organic dielectric film 12 is enhanced in adhesion to the work 10 by chemical bonding. Inverse sputtering is carried out by the use of rare gas such as He, Ar, Xe, Kr or the like. Reducing gas such as H2, SiH4 or the like may be added to these rare gases. Inverse sputtering is carried out in the same film forming chamber where an inorganic dielectric film 11a is formed, or an inverse sputtering is carried out in an inverse sputtering- dedicated pre-treatment chamber. In this case, a pre-treatment chamber and a film forming chamber are continuously connected through a vacuum gate valve, and a metal wiring provided on a work is prevented from being oxidized again while the work is trarsferred.

    FORMING METHOD FOR METAL-BASED FILM AND MANUFACTURE OF ELECTRONIC DEVICE

    公开(公告)号:JP2000124307A

    公开(公告)日:2000-04-28

    申请号:JP29699098

    申请日:1998-10-19

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To prevent contamination of a metal-based film, deterioration of a film-forming shape, or the like that are caused by degassing from an organic macromolecule material, when the metal-based film is formed on a substrate to be treated which contains the organic macromolecule material having low dielectric constant. SOLUTION: A substrate to be treated is heat-treated at a temperature that is at least the degassing start temperature and is lower than thermal decomposition start temperature of an organic macromolecule material 11 in non-oxidizing atmosphere. After this, a metal-based film 16 is formed at a film-forming temperature that is lower than the heat treatment temperature. When the substrate to be treated is not heat-treated, the metal-based film 16 may be formed at a film-forming temperature that is lower than the degassing start temperature.

    LOW-DIELECTRIC CONST. RESIN COMPSN., METHOD OF FORMING LOW-DIELECTRIC CONST. INSULATION FILM AND MANUFACTURING SEMICONDUCTOR DEVICE

    公开(公告)号:JP2000021872A

    公开(公告)日:2000-01-21

    申请号:JP23310898

    申请日:1998-08-19

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To provide an insulation film material having a superior heat resistance and low dielectric const. by means that a low dielectric const. resin compsn. for insulation films of a semiconductor device contains an Si-based porous film material and low dielectric const. film material. SOLUTION: The low dielectric const. resin compsn. for insulation films of a semiconductor device contains as an Si-based porous film material at least one of alkoxysilane polymers shown by a general formula RpSi(OR)4-p, pref. at least one of alkoxysilane compd. polymers shown by a general formula 1-10 wt.% and diluent wherein R is alkyl group, including substd. groups, R' is alkyl group, p is 0, 1 or 2, and when p is 2, R may be the same or different from each other. Thus it is possible to form a low dielectric const. insulation film having a low dielectric const. and superior heat resistance, resulting in that the capacitance between wirings is remarkably reduced and a semiconductor device superior in heat resistance is obtd.

    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

    公开(公告)号:JPH11233630A

    公开(公告)日:1999-08-27

    申请号:JP3622098

    申请日:1998-02-18

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To prevent an easy-to-oxidize metal wire of Cu, etc., from oxidizing, when a connecting hole is bored in an organic insulating film on the metal wire. SOLUTION: On a 1st layer meal wire 5, an inorganic insulating film 6 is formed thin, and then a lower-layer organic insulating film 7 and an upper-layer organic insulating film 8 are formed thereupon. Then those organic insulating films are patterned, and then the inorganic insulating film is patterned so as to complete the boring of a connection hole 9. Consequently, oxygen-based active seeds needed for patterning the organic insulating films are prevented from coming into contact with the metal wire in the final boring process of the connection hole. A semiconductor device of a high-speed logic system, etc., requiring a low-resistance wire and a low-permittivity interlayer insulating film can be manufactured with high reliability.

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