公开(公告)号：JPH07221208A

公开(公告)日：1995-08-18

申请号：JP3547894

申请日：1994-02-08

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To prevent carriers from being extracted from a floating gate to a control gate when data are written, and prevent the state from being mistaken for the erase state when data are read. CONSTITUTION:When a writing voltage is low, data can be written through a channel 21a whose threshold voltage is low. The channel region 21a is arranged in series between a channel region 21b whose threshold voltage is high and a source 12/a drain 13. Thereby, when the channel region 21a is turned into the depletion type by excessive erase of data, the memory cell can be turned into the enhancement type by turning the channel region 21b into the enhancement type.

公开(公告)号：JPH06350095A

公开(公告)日：1994-12-22

申请号：JP16016193

申请日：1993-06-04

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To realize low voltage without increasing a chip area by constructing a split gate structure without enlarging a memory cell area. CONSTITUTION:An enhancement gate 32 is formed by making a SiO2 14b on the side wall of a tungsten polycide 37 in a trench 36 thicker than a SiO2 on the bottom. A SiO2 41 fills out the top of the tungsten polycide 37, and a contact hole 24 and an opening 44 are positioned on the tungsten polycide 37. As a result, a memory cell area does not only increase but can be reduced instead.

公开(公告)号：JPH06104170A

公开(公告)日：1994-04-15

申请号：JP21148091

申请日：1991-07-29

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: G03F7/26 ,  H01L21/027

Abstract: PURPOSE:To reduce etching irregularities in each pattern by performing similar etching for the separately opened patterns. CONSTITUTION:A multilayer resist structure provided with a lower resist 2, a second intermediate layer 32, a first intermediate layer 31 and a first upper resist 41 one by one from the side of a substrate on a substrate 1 wherein a pattern is to be formed, and the first upper resist 41 is patterned. The first intermediate layer 31 is patterned using the acquired first upper resist pattern 41a as a mask. After a first upper resist pattern is removed, a second upper resist 42 is formed. The second upper resist is patterned and the first intermediate layer 31 is patterned using the acquired second upper resist pattern 42a as a mask. Patterns such as (a), (b), (c) are opened and etched by repeating the above processes successively.

公开(公告)号：JPH0628281B2

公开(公告)日：1994-04-13

申请号：JP20624783

申请日：1983-11-02

Applicant: SONY CORP

Inventor： HAYASHI YASUO ,  NAKAJIMA HIDEHARU ,  KAYAMA SHIGEKI ,  SHIMADA TAKASHI

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/318 ,  H01L21/762

公开(公告)号：JPH0425173A

公开(公告)日：1992-01-28

申请号：JP12967690

申请日：1990-05-19

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L27/11 ,  H01L21/8244

Abstract: PURPOSE:To lessen a semiconductor memory in number of manufacturing processes by a method wherein the gate electrode of a semiconductor memory provided with a buried gate is provided at a position lower than the surface of a substrate, and a semiconductor layer is formed on a source-drain lead-out wiring layer to constitute a thin film transistor. CONSTITUTION:A gate electrode 3 is buried at a position lower than the surface 4 of a substrate as covered with an insulating film 5, and a source region 6 and a drain region 7 are formed on the surface 4 of the substrate sandwiching the gate electrode 3 between them. A wiring layer 10 connected to the source region 6 and the drain region 7 is covered with a thin insulating film 11, and a thin film transistor is formed taking advantage of a semiconductor layer 12 deposited on the insulating film 11. That is, the gate electrode 3 is formed in a substrate at a position deeper than the surface 4 of the substrate 1, and the wiring layer 10 connected to the source region 6 and the drain region 7 is used for a thin film transistor as it is. By this setup, a memory cell high in degree of integration can be obtained without increasing manufacturing processes in number.

公开(公告)号：JPH0341772A

公开(公告)日：1991-02-22

申请号：JP17672789

申请日：1989-07-07

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L29/78

Abstract: PURPOSE:To enable the title semiconductor device to be miniaturized by a method wherein the surface of a gate electrode near the surface of a semiconductor substrate is positioned inside the semiconductor substrate. CONSTITUTION:Even if a contact window 18a opposite to a source drain region 15a and a gate electrode 17 are seen as if in contact with each other at the same level, a wiring 21 and a gate 17 opposite to a source drain region 15a are isolated from each other by at least the length between the surface of the gate electrode 17 near a semiconductor substrate 13 and the surface of the semiconductor substrate 13. Furthermore, the gate electrode 17 looks planar when seen from the wiring 21 opposite to the source drain region 15a so as to lessen the fringe effect. Accordingly, the electric field between the wiring 21 opposite to the source drain region 15a and the gate electrode 17 is weak so that specified dielectric strength may be gained even if the contact window 18a opposite to the source drain region 15a and the gate electrode 17 are approached with each other at the same level.

公开(公告)号：JPH0239540A

公开(公告)日：1990-02-08

申请号：JP18974188

申请日：1988-07-29

Applicant: SONY CORP

Inventor： KOBAYASHI KAZUYOSHI ,  SHIMADA TAKASHI

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

Abstract: PURPOSE:To make it possible to prevent deterioration or breakdown of a gate insulating film arising at removal of a resist film or at ion implantation by forming a conductive layer on a film on a gate insulating film so as to form a gate electrode with the film and the conductive layer. CONSTITUTION:After forming a field insulating layer 2 and a gate insulating film 3, a thin impurity-doped polycrystalline silicon film 4 is formed. Next, ions of, for example, boron B are implanted into the surface part of a semiconductor region 1 through the gate insulating film 3 and the polycrystalline silicon film 4 so as to form an ion implanted region 5 for controlling the threshold voltage Vth. Further, ions of impurity of the same conductivity as the semiconductor region 1 are implanted into the lower part of a channel region formation part so as to form an ion implanted layer 6 in high impurity concentration to suppress the expansion of a depletion layer. Next, an impurity-doped polycrystalline silicon layer 7 constituting a silicon gate electrode, etc., is formed on the whole surface of the film 4. Next, after formation of a silicon gate electrode 8, ions of impurity are implanted into a the semiconductor region 1 with the field insulating film 2 and the gate electrode 8 as a mask so as to form a source region 9 and a drain region 10.

公开(公告)号：JPS6159539B2

公开(公告)日：1986-12-17

申请号：JP9902976

申请日：1976-08-19

Applicant: SONY CORP

Inventor： OOTSU KOJI ,  MOCHIZUKI HIDENOBU ,  SHIMADA TAKASHI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78

公开(公告)号：JPS61214473A

公开(公告)日：1986-09-24

申请号：JP5338485

申请日：1985-03-19

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L29/78 ,  H01L21/265

Abstract: PURPOSE:To minimize field concentration while inhibiting the reduction of mutual conductance gm by forming a low impurity-concentration region adjacent to a gate electrode in a surface region in a substrate and also shaping a high impurity-concentration region adjacent to the low impurity-concentration region under the low impurity-concentration region while being adjoined to the low impurity-concentration region. CONSTITUTION:A low impurity-concentration region 5 is formed to a section adjacent to a gate electrode 4 in a surface region in a semiconductor substrate 7. A high impurity-concentration region adjacent to the low impurity- concentration region 5 is also shaped under the low impurity-concentration region 5 while being adjoined to the region 5 in the region 9 deeper than the surface region in the substrate 7. Consequently, currents can flow in the vertical direction (the direction of the arrow (a)). Accordingly, the resistance of source- drain can be minimized, and the reduction rate of mutual conductance gm thereof can be decreased.

公开(公告)号：JPS61120460A

公开(公告)日：1986-06-07

申请号：JP24173384

申请日：1984-11-16

Applicant: Sony Corp

Inventor： NAIKI TADAHACHI ,  HARADA YOSHIO ,  SHIMADA TAKASHI

IPC: H01L27/08 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/8238

Abstract: PURPOSE:To provide a stop region without position deviation, by utilizing oxidation resisting films, which are provided in a photoresist layer at the time of forming a well and an element forming region in the well beforehand, as mask to be used, when the channel stopping region is formed in the well region of a complementary MOS.IC and performing self-alignment. CONSTITUTION:A thin SiO2 film 32 is deposited on the surface of an n type Si substrate 3. Oxidation resisting films 33 and 34 comprising Si3N4 are provided in correspondence with a p-channel MOS transistor and an n-channel MOS transistor. The films 33 on both sides of the film 34 are surrounded by photoresist 35. Then, p type impurity ions are implanted in the substrate 31 located between the layers 35. A p type well region 36 is formed with the remaining film 34 and the layer 35 as mask, p type impurity ions are implanted in both end parts of the region 36, and a p type channel stop region 37 is provided. Thereafter, element regions having different channels are formed in the region 36 and the part neighboring the region 36.

Abstract translation: 目的：为了提供没有位置偏差的停止区域，通过利用在预先形成阱中的光致抗蚀剂层中设置在光致抗蚀剂层中的抗氧化膜，作为所使用的掩模，当通道 在互补MOS.IC的阱区域中形成停止区域并执行自对准。 构成：在n型Si衬底3的表面上沉积薄的SiO 2膜32.与p沟道MOS晶体管和n沟道MOS晶体管相对应地设置包含Si 3 N 4的氧化阻挡膜33和34。 膜34两侧的膜33被光致抗蚀剂35包围。然后，将p型杂质离子注入到位于层35之间的衬底31中。形成p型阱区36，剩余的膜34和层 35作为掩模，在区域36的两端部注入p型杂质离子，设置ap +型沟道停止区域37。 此后，在区域36和与区域36相邻的部分形成具有不同通道的元件区域。